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Advanced v0.5
ProASIC3 Flash Family FPGAs
ARM7
TM
(R)
Soft IP Support in ProASIC3 ARM7-Ready Devices
* * * * * * * * * * * * Architecture Supports Ultra-High Utilization 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages - Up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/ 2.5 V/ 1.8 V/1.5 V, 3.3 V PCI/3.3 V PCI-X (except A3P030), and LVCMOS 2.5 V/5.0 V Input Differential I/O Standards: LVPECL and LVDS (A3P250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold Sparing I/Os (A3P030 only) Programmable Output Slew Rate (except A3P030) and Drive Strength Weak Pull-Up/Down IEEE1149.1 (JTAG) Boundary Scan Test Pin-Compatible Packages Across the ProASIC3 Family
Features and Benefits
High Capacity
* * * * * * * * * * * * * * * * * * * 30 k to 1 Million System Gates Up to 144 kbits of True Dual-Port SRAM Up to 300 User I/Os 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live At Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off 1 kbit of FlashROM (FROM) 350 MHz System Performance 3.3 V, 66 MHz 64-Bit PCI (except A3P030) Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except A3P030) via JTAG (IEEE1532-compliant) FlashLock(R) to Secure FPGA Contents 1.5 V Core Voltage for Low Power Support for 1.5-V-Only Systems Low-Impedance Flash Switches Segmented, Hierarchical Routing and Clock Structure Ultra-Fast Local and Long-Line Network Enhanced High-Speed, Very-Long-Line Network High-Performance, Low-Skew Global Network
Advanced I/O
Reprogrammable Flash Technology
On-Chip User Nonvolatile Memory High Performance In-System Programming (ISP) and Security
Clock Conditioning Circuit (CCC) and PLL (except A3P030)
* * * * * * Six CCC Blocks, One with an Integrated PLL Flexible Phase-Shift, Multiply/Divide, and Delay Capabilities Wide Input Frequency Range (1.5 MHz to 350 MHz) Variable-Aspect Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, x18 Organizations Available) True Dual-Port SRAM (except x18) 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz Soft Core Support in ARM7-Ready Devices
Low Power
SRAMs and FIFOs (except A3P030)
High-Performance Routing Hierarchy
ARM7 Processor
*
Table 1 *
ProASIC3 Product Family
A3P030 A3P060 A3P125 A3P250 M7A3P250 250 k 6,144 36 8 1k Yes 1 18 4 157 A3P400 M7A3P400 400 k 9,216 54 12 1k Yes 1 18 4 194 A3P600 M7A3P600 600 k 13,824 108 24 1k Yes 1 18 4 227 A3P1000 M7A3P1000 1M 24,576 144 32 1k Yes 1 18 4 300
ProASIC3 Devices ARM7-Ready ProASIC3 Devices1 System Gates VersaTiles (D-Flip-Flops) RAM kbits (1,024 bits) 4,608 Bit Blocks FlashROM (FROM) Bits Secure (AES) ISP2 Integrated PLL in CCCs VersaNet Globals3 I/O Banks Maximum User I/Os Package Pins QFN VQFP TQFP PQFP FBGA
30 k 768 - - 1k - - 6 2 81 QN132 VQ100
60 k 1,536 18 4 1k Yes 1 18 2 96
125 k 3,072 36 8 1k Yes 1 18 2 133
VQ100 TQ144 FG144
VQ100 TQ144 PQ208 FG144
VQ100 PQ208 FG144, FG2565 PQ208 FG144, FG256, FG484 PQ208 FG144, FG256, FG484 PQ208 FG144, FG256, FG484
Notes: 1. Refer to the CoreMP7 datasheet for more information. 2. AES is not available for ARM7-ready ProASIC3 devices. 3. Six chip (main) and three quadrant global networks are available for A3P060 and above. 4. For higher densities and support of additional features, refer to the ProASIC3E Flash FPGAs datasheet. 5. This package is not supported for the M7A3P250 device.
January 2006 (c) 2006 Actel Corporation i See the Actel website for the latest version of the datasheet.
ProASIC3 Flash Family FPGAs
I/Os Per Package
ProASIC3 Devices ARM7-Ready ProASIC3 Devices A3P030 A3P060 A3P125 A3P250 2 A3P400 2 A3P600 A3P1000
M7A3P2504 Differential I/O Pairs Single-Ended I/O1
M7A3P400 Differential I/O Pairs Single-Ended I/O1
M7A3P600 Differential I/O Pairs Single-Ended I/O1
M7A3P1000 Differential I/O Pairs - - - 35 25 44 74 Single-Ended I/O1 - - - 154 97 177 300
Single-Ended I/O
Single-Ended I/O
Package QN132 VQ100 TQ144 PQ208 FG144 FG256 FG484 Notes:
81 79 - - - - -
- 71 91 - 96 - -
Single-Ended I/O - 71 100 133 97 - -
- 68 - 151 97 157 -
- 13 - 34 24 38 -
- - - 151 97 178 194
- - - 33 24 38 38 - 154 97 179 227
- - - 35 24 45 56
1. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 2. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to "Package Pin Assignments" starting on page 4-1 for position assignments of the 15 LVPECL pairs. 3. FG256 and FG484 are footprint-compatible packages. 4. The FG256 package is not supported for the M7A3P250 device.
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ProASIC3 Ordering Information
A3P1000 _ 1 FG G 144 I Application (Ambient Temperature Range) Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS Compliant (Green) Packaging Package Type QN = Quad Flat Pack No Leads (0.5 mm pitch) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) TQ = Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade F = 20% Slower than Standard* Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard
Part Number ProASIC3 Devices
A3P030 = 30,000 System Gates A3P060 = 60,000 System Gates A3P125 = 125,000 System Gates A3P250 = 250,000 System Gates A3P400 = 400,000 System Gates A3P600 = 600,000 System Gates A3P1000 = 1,000,000 System Gates M7-Ready ProASIC3 Devices M7A3P030 = 30,000 System Gates M7A3P060 = 60,000 System Gates M7A3P125 = 125,000 System Gates M7A3P250 = 250,000 System Gates M7A3P400 = 400,000 System Gates M7A3P600 = 600,000 System Gates M7A3P1000 = 1,000,000 System Gates
Note: *-F Speed Grade - DC and switching based only on simulation. The characteristics are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. This speed grade is only supported in commercial temperature range.
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ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
A3P030 Package QN132 VQ100 TQ144 PQ208 FG144 FG256 FG484 C, I C, I - - - - - - C, I C, I - C, I - - - C, I C, I C, I C, I - - A3P060 A3P125 A3P250 M7A3P250 - C, I - C, I C, I C, I - A3P400 M7A3P400 - - - C, I C, I C, I C, I A3P600 M7A3P600 - - - C, I C, I C, I C, I A3P1000 M7A3P1000 - - - C, I C, I C, I C, I
Note: C = Commercial Temperature Range: 0C to 70C Ambient I = Industrial Temperature Range: -40C to 85C Ambient
Speed Grade and Temperature Grade Matrix
-F 3 C I Notes: 1. C = Commercial Temperature Range: 0C to 70C Ambient 2. I = Industrial Temperature Range: -40C to 85C Ambient 3. DC and switching characteristics for -F speed grade targets based only on simulation. The characteristics provided for -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in commercial temperature range. - Std. -1 -2
Datasheet references made to ProASIC3 devices also apply to ARM7-ready ProASIC3 devices. The part numbers start with M7. Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).
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ProASIC3 Flash Family FPGAs
Device Architecture
Introduction and Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Device Architecture
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 Embedded FROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
Package Pin Assignments
132-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 256-Pin FBGA 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
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ProASIC3 Flash Family FPGAs
Introduction and Overview
General Description
ProASIC3, the third-generation family of Actel Flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS(R) family. The nonvolatile Flash technology gives ProASIC3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up. ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM (FROM) memory storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P030 device has no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM, and up to 288 user I/Os. ProASIC3 devices support the ARM7 soft IP core in devices with at least 250 k system gates. The ARM7-ready devices have Actel ordering numbers that begin with M7A3P and do not support AES decryption. FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile, Flash programming can offer. ProASIC3 devices utilize a 128-bit Flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FROM data in the ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000, and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES decryption engine and a Flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure design verification is possible. ARM7-ready ProASIC3 devices support all security measures except for AES decryption. Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The Flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. ProASIC3, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. A ProASIC3 device provides the most impenetrable security for programmable logic designs.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low-unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, the Flash-based ProASIC3 devices allow for all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets.
Single Chip
Flash-based FPGAs store the configuration information in on-chip Flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, Flashbased ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load the device configuration data. This reduces bill-of-materials costs and printed circuit board (PCB) area, and increases security and system reliability.
Security
The nonvolatile, Flash-based ProASIC3 devices require no boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate
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ProASIC3 Flash Family FPGAs
Live at Power-Up
The Actel Flash-based ProASIC3 devices support Level 0 of the live at power-up (LAPU) classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of Flash-based ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for Complex Programmable Logic Devices (CPLDs) and clock generation PLLs that are used for this purpose in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's Flash configuration, and unlike SRAMbased FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flashbased ProASIC3 devices simplify total system design, and reduce cost and design risk, while increasing system reliability and improving system initialization time. Refer to the "I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)" section on page 3-3.
ProASIC3 devices also have low dynamic power consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an advanced Flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant Flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-3 and Figure 1-2 on page 1-3): * * * * * FPGA VersaTiles Dedicated FlashROM (FROM) memory Dedicated SRAM/FIFO memory1 Extensive clock conditioning circuitry (CCC) and PLLs1 Advanced I/O structure
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 Flashbased FPGAs. Once it is programmed, the Flash cell configuration element of ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current surge, and no high-current transition period, both of which occur on many FPGAs.
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function or as a D-flip-flop (with or without enable), or as a latch by programming the appropriate Flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input look-up-table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC families of Flash-based FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of the ProASIC3 devices via an IEEE1532 JTAG interface.
1. The APA030 does not support PLL and SRAM.
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ProASIC3 Flash Family FPGAs
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block*
Bank 1
Bank 0 Bank 0
I/Os
VersaTile
Bank 1
ISP AES Decryption*
User Nonvolatile FlashROM (FROM) Bank 1
Charge Pumps
Note: *Not supported by A3P030. Figure 1-1 * Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125)
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block
Bank 3
Bank 1 Bank 1
I/Os
VersaTile
Bank 3
ISP AES Decryption
User Nonvolatile FlashROM (FROM) Bank 2
Charge Pumps
RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600 and A3P1000)
Figure 1-2 * Device Architecture Overview with Four I/O Banks (A3P250, A3P400, A3P600, and A3P1000)
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ProASIC3 Flash Family FPGAs
VersaTiles
The ProASIC3 core consists of VersaTiles, which have been enhanced from the ProASICPLUS core tiles. The ProASIC3 VersaTile supports the following: * * * * All three-input logic functions - LUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations. For more information about VersaTiles, refer to the "VersaTile" section on page 2-2.
LUT-3 Equivalent X1 X2 X3
D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF
Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y
LUT-3
Y
Figure 1-3 * VersaTile Configurations
User Nonvolatile FlashROM (FROM)
Actel ProASIC3 devices have 1 kbit of on-chip, useraccessible, nonvolatile FlashROM (FROM). The FROM can be used in diverse system applications: * * * * * * * * Internet protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management
byte basis. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FROM address determine the bank, and the four least significant bits (LSBs) of the FROM address define the byte. The Actel ProASIC3 development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer v6.1 or later, have extensive support for the FROM memory. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. The second part allows the inclusion of static data for system version control. Data for the FROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FROM contents.
The FROM is written using the standard ProASIC3 IEEE1532 JTAG programming interface. The core can be individually programmed (erased and written), and onchip AES decryption can be used selectively to securely load data over public networks (except in the A3P030 device), such as security keys stored in the FROM for a user design. The FROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FROM can ONLY be programmed from the JTAG interface, and cannot be programmed from the internal logic array. The FROM is programmed as 8 banks of 128 bits; however, reading is performed on a random byte-by-
SRAM and FIFO
ProASIC3 devices (except in the A3P030 device) have embedded SRAM blocks along the north and south sides of the device. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, or 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode), using the UJTAG macro (except for the A3P030
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device). For more information, refer to the application note, UJTAG Applications in ProASIC3/E Devices. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for the generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
* * * *
Maximum acquisition time = 150 s (for PLL only) Low power consumption of 5 mW Exceptional tolerance to input period jitter - allowable input jitter is up to 1.5 ns (for PLL only) Four precise phases; maximum misalignment between adjacent phases of 40 ps x (350 MHz / fOUT_CCC) (for PLL only)
Global Clocking
ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks (Figure 2-10 on page 2-11). The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets.
PLL and Clock Conditioning Circuitry (CCC)
ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL (Figure 2-10 on page 2-11). The A3P030 does not have a PLL. The six CCC blocks are located in the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access (refer to the "Clock Conditioning Circuits" section on page 2-15 for more information). The inputs of the six CCC blocks are accessible from the FPGA core or from one of several I/O inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has the following key features: * * * * Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz Clock delay adjustment via programmable and fixed delays from -7.56 ns to +11.12 ns Two programmable delay types; refer to Figure 2-17 on page 2-19, Table 2-4 on page 2-20, and the "Features Supported on Every I/O" section on page 2-31 for more information. Clock skew minimization Clock frequency synthesis (for PLL only) Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). Output duty cycle = 50% 1.5% or better (for PLL only) Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only)
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards: single-ended and differential. For more information, see Table 2-19 on page 2-45. The I/Os are organized into banks, with two or four banks per device. Refer to Table 2-18 on page 2-44 for details on I/O bank configuration. The configuration of these banks determines the I/O standards supported (see Table 2-18 on page 2-44 for more information). Each I/O module contains several input, output, and enable registers (Figure 2-23 on page 2-32). These registers allow the implementation of the following: * * Single-Data-Rate applications Double-Data-Rate applications - DDR LVDS I/O for point-to-point communications
* * *
Additional CCC specifications:
* *
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Related Documents
Application Notes
In-System Programming (ISP) in ProASIC3/E Using FlashPro3 http://www.actel.com/documents/PA3_E_ISP_AN.pdf ProASIC3/E FlashROM (FROM) http://www.actel.com/documents/PA3_E_FROM_AN.pdf ProASIC3/E Security http://www.actel.com/documents/PA3_E_Security_AN.pdf ProASIC3/E SRAM/FIFO Blocks http://www.actel.com/documents/PA3_E_SRAMFIFO_AN.pdf Programming a ProASIC3/E Using a Microprocessor http://www.actel.com/documents/PA3_E_Microprocessor_AN.pdf UJTAG Applications in ProASIC3/E Devices http://www.actel.com/documents/PA3_E_UJTAG_AN.pdf Using DDR for ProASIC3/E Devices http://www.actel.com/documents/PA3_E_DDR_AN.pdf Using Global Resources in Actel ProASIC3/E Devices http://www.actel.com/documents/PA3_E_Global_AN.pdf Power-Up/Down Behavior of ProASIC3/E Devices http://www.actel.com/documents/ProASIC3_E_PowerUp_AN.pdf For additional ProASIC3 application notes, go to http://www.actel.com/techdocs/appnotes/products.aspx.
User's Guides
ACTgen Cores Reference Guide http://www.actel.com/documents/gen_refguide_ug.pdf Designer User's Guide http://www.actel.com/documents/designer_ug.pdf ProASIC3/E Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf
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ProASIC3 Flash Family FPGAs
Device Architecture
Introduction
Flash Technology
Advanced Flash Switch
Unlike SRAM FPGAs, the ProASIC3 family uses a live on power-up ISP Flash switch as its programming element. Flash cells are distributed throughout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate VersaTile inputs and outputs. In the Flash switch, two transistors share the floating gate, which stores the programming information (Figure 2-1). One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. The latter is used to connect or separate routing nets, or to configure VersaTile logic. It is also used to erase the floating gate. Dedicated highperformance lines are connected as required using the Flash switch for fast, low-skew, global signal distribution throughout the device core. Maximum core utilization is possible for virtually any design. The use of the Flash switch technology also removes the possibility of firm errors, which are increasingly common in SRAM-based FPGAs.
Floating Gate
Switch In
Sensing
Switching
Word Switch Out
Figure 2-1 * ProASIC3 Flash-Based Switch
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ProASIC3 Flash Family FPGAs
Device Overview
The ProASIC3 device family consists of five distinct programmable architectural features (Figure 2-2 and Figure 2-3 on page 2-3): * * * * * FPGA fabric/core (VersaTiles) Routing and clock resources (VersaNets) FlashROM (FROM) memory Dedicated SRAM/FIFO memory (except A3P030) Advanced I/O structure
* * * *
Any three-input logic function Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set (on a fourth input)
VersaTiles can flexibly map the logic and sequential gates of a design. The inputs of the VersaTile can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line routing resources. VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. When the VersaTile is used as an enable D-flip-flop, the SET/CLR is supported by a fourth input. The fourth input is routed to the core cell over the VersaNet (global) network. The SET/CLR signal can only be routed to this fourth input over the VersaNet (global) network. However, if in the user design, the SET/CLR signal is not routed over the VersaNet network, a compile warning message will be given and the intended logic function will be implemented by two VersaTiles instead of one. The output of the VersaTile is F2 when the connection is to the ultra-fast local lines, or YL when the connection is to the efficient long-lines or very-long-lines resources.
Core Architecture
VersaTile
The proprietary ProASIC3 family architecture provides granularity comparable to gate arrays. The ProASIC3 device core consists of a sea-of-VersaTiles architecture. As illustrated in Figure 2-4 on page 2-4, there are four inputs in a logic VersaTile cell, and each VersaTile can be configured using the appropriate Flash switch connections:
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block*
Bank 1
Bank 0 Bank 0
I/Os
VersaTile
Bank 1
ISP AES Decryption*
User Nonvolatile FlashROM (FROM) Bank 1
Charge Pumps
Note: *Not supported by A3P030. Figure 2-2 * Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125)
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Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block
Bank 3
Bank 1 Bank 1
I/Os
VersaTile
Bank 3
ISP AES Decryption
User Nonvolatile FlashROM (FROM) Bank 2
Charge Pumps
RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600 and A3P1000)
Figure 2-3 * Device Architecture Overview with Four I/O Banks (A3P250, A3P400, A3P600, A3P1000)
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0 1 Data X3 Y pin 1 0 1 0 1 F2
YL 0 1 CLK X2
CLR/ Enable X1 CLR XC*
Legend:
Via (hard connection)
Switch (Flash connection)
Ground
Note: *This input can only be connected to the global clock distribution network. Figure 2-4 * ProASIC3 Core VersaTile
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ProASIC3 Flash Family FPGAs
Array Coordinates
During many place-and-route operations in the Actel Designer software tool, it is possible to set constraints that require array coordinates. Table 2-1 is provided as a reference. The array coordinates are measured from the lower left (0, 0). They can be used in region constraints for specific logic groups/blocks, designated by a wildcard, and can contain core cells, memories, and I/Os. Table 2-1 provides array coordinates of core cells and memory blocks. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O cells and core cells. In addition, the I/O coordinate system
Table 2-1 * ProASIC3 Array Coordinates VersaTiles Min. Device A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 x - 3 3 3 3 3 3 y - 2 2 2 2 4 4 x - 66 130 130 194 194 258 Max. y - 25 25 49 49 75 99 Memory Rows Bottom (x, y) - None None None None (3, 2) (3, 2) Top (x, y) - (3, 26) (3, 26) (3, 50) (3, 50) (3, 76) (3, 100) Min. (x, y) - (0, 0) (0, 0) (0, 0) (0, 0) (0, 0) (0, 0) All Max. (x, y) - (69, 29) (133, 29) (133, 53) (197, 53) (197, 79) (261, 103)
changes depending on the die/package combination. It is not listed in Table 2-1. The Designer ChipPlanner tool provides array coordinates of all I/O locations. I/O and cell coordinates are used for placement constraints. However, I/O placement is easier by package pin assignment. Figure 2-5 on page 2-6 illustrates the array coordinates of an A3P600 device. For more information on how to use array coordinates for region/placement constraints, see the Designer User's Guide or online help (available in the software) for ProASIC3 software tools.
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I/O Tile
(0, 79) Top Row (7, 79) to (189, 79) Bottom Row (5, 78) to (192, 78) (197, 79)
Memory (3, 77) Blocks (3, 76) VersaTile (Core) (3, 75)
(194, 77) Memory (194, 76) Blocks
(194, 75) VersaTile (Core)
VersaTile (Core) (3, 4) Memory (3, 3) Blocks (3, 2)
(194, 4) VersaTile(Core) (194, 3) Memory (194, 2) Blocks
(197, 1) (0, 0)
I/O Tile
Top Row (5, 1) to (168, 1) Bottom Row (7, 0) to (165, 0)
UJTAG FlashROM Top Row (169, 1) to (192, 1)
(197, 0)
Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. Figure 2-5 * Array Coordinates for A3P600
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Routing Architecture
Routing Resources The routing structure of ProASIC3 devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very-long-line resources, and the high-performance VersaNet networks. The ultra-fast local resources are dedicated lines that allow the output of each VersaTile to connect directly to every input of the eight surrounding VersaTiles (Figure 2-6). The exception to this is that the SET/CLR input of a VersaTile configured as a D-type flip-flop is driven only by the VersaTile global network. The efficient, long-line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 VersaTiles), run both vertically and horizontally, and cover the entire ProASIC3 device (Figure 2-7 on page 2-8). Each VersaTile can drive signals onto the efficient long-line resources, which can access every input of every VersaTile. Active buffers are inserted automatically by routing software to limit the loading effects.
The high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length +/-12 VersaTiles in the vertical direction and length +/-16 in the horizontal direction from a given core VersaTile (Figure 2-8 on page 2-9). Very long lines in ProASIC3 devices have been enhanced over those in previous ProASIC families. This provides a significant performance boost for long-reach signals. The high-performance VersaNet global networks are low-skew, high-fanout nets that are accessible from external pins or from internal logic (Figure 2-9 on page 2-10). These nets are typically used to distribute clocks, resets, and other high-fanout nets requiring minimum skew. The VersaNet networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all VersaTiles.
Long Lines
L
L
L
L
Inputs
L
Output
L Ultra-Fast Local Lines (connects a VersaTile to the adjacent VersaTile, I/O buffer, or memory block) L
L
L
Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection. Figure 2-6 * Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors
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Spans Four VersaTiles
Spans Two VersaTiles
Spans One VersaTile Logic VersaTile
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Spans One VersaTile Spans Two VersaTiles Spans Four VersaTiles
L
L
L
L
L
L
VersaTile
L L L L L L
Figure 2-7 * Efficient Long-Line Resources
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High-Speed, Very-Long-Line Resources Pad Ring
SRAM I/O Ring 16x12 Block of VersaTiles I/O Ring Pad Ring
Pad Ring
Figure 2-8 * Very-Long-Line Resources
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Clock Resources (VersaNets)
ProASIC3 devices offer powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has up to six CCCs. The west CCC also contains a phase-locked loop (PLL) core, delay lines, phase shifter (0, 90, 180, 270), and clock multiplier/dividers. Each CCC has all the circuitry needed for the selection and interconnection of inputs to the VersaNet global network. The east and west CCCs each have access to three VersaNet global lines on each side of the chip (six total lines). The CCCs at the four corners each have access to three Quadrant global lines on each quadrant of the chip (except A3P030).
Advantages of the VersaNet Approach One of the architectural benefits of ProASIC3 is the set of powerful and low-delay VersaNet global networks. ProASIC3 offers six chip (main) global networks that are distributed from the center of the FPGA array (Figure 2-9). In addition, ProASIC3 devices have three regional globals in each of the four chip quadrants. Each core VersaTile has access to nine global network resources: three quadrant and six chip (main) global networks, and a total of 18
Quadrant Global Pads Pad Ring
globals on the device. Each of these networks contains spines and ribs that reach all the VersaTiles in the quadrants (Figure 2-10 on page 2-11). This flexible VersaNet global network architecture allows users to map up to 144 different internal/external clocks in a ProASIC3 device. Details on the VersaNet networks are given in Table 2-2 on page 2-11. The flexible use of the ProASIC3 VersaNet global network allows the designer to address several design requirements. User applications that are clock-resourceintensive can easily route external or gated internal clocks using VersaNet global routing networks. Designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the VersaNet global network. In A3P030 devices, all six VersaNets are driven from three southern I/Os, located toward the east and west sides. These tiles can be configured to select a central I/O on the respective side or an internal routed signal as the input signal. The A3P030 does not support any clock conditioning circuitry nor does it contain the VersaNet global network concept of top and bottom spines.
High-Performance VersaNet Global Network
Pad Ring
I/O Ring
Top Spine
Main (chip) Global Network Chip (main) Global Pads Global Pads Global Spine Bottom Spine Global Ribs
I/O Ring
Spine-Selection Tree MUX
Pad Ring
Note: Not applicable to the A3P030 device. Figure 2-9 * Overview of ProASIC3 VersaNet Global Network
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Northwest Quadrant Global Network CCC Quadrant Global Spine 3 3 3 3 CCC
6 3
Chip (main) Global Network 6
6
6 3 CCC
CCC Global Spine 6 6 6 6
3 CCC
3
3
3 CCC
Southeast Quadrant Global Network
Note: This does not apply to the A3P030 device. Figure 2-10 * Global Network Architecture Table 2-2 * ProASIC3 Globals/Spines/Rows by Device A3P030 Global VersaNets (Trees)* VersaNet Spines/Tree Total Spines VersaTiles in Each Top or Bottom Spine Total VersaTiles Rows in Each Top or Bottom Spine 6 4 24 384 768 - A3P060 9 4 36 384 1,536 12 A3P125 9 4 36 384 3,072 12 A3P250 9 8 72 768 6,144 24 A3P400 9 8 72 768 9,216 24 A3P600 9 12 108 1,152 13,824 36 A3P1000 9 16 144 1,536 24,576 48
Note: *There are six chip (main) globals and three globals per quadrant (except in the A3P030 device).
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ProASIC3 Flash Family FPGAs
VersaNet Global Networks and Spine Access The ProASIC3 architecture contains a total of 18 segmented global networks that can access the VersaTiles, SRAM memory, and I/O tiles on the ProASIC3 device. There are nine global network resources in each device quadrant: three quadrant globals and six chip (main) global networks. Each device has a total of 18 globals. These VersaNet global networks offer fast, lowskew routing resources for high-fanout nets, including clock signals. In addition, these highly-segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 144 internal/ external clocks (in an A3P1000 device) or other highfanout nets in ProASIC3 devices. Optimal usage of these low-skew networks can result in significant improvement in design performance on ProASIC3 devices. The nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global network, which has six spines. Note that there are three quadrant spines in each quadrant of the device (except for A3P030). There are four quadrant global network regions per device (Figure 2-10 on page 2-11). The spines are the vertical branches of the global network tree, shown in Figure 2-11 on page 2-13. Each spine in a vertical column of a chip (main) global network is further divided into two equal-length spine segments: one in the top and one in the bottom half of the die.
Each spine and its associated ribs cover a certain area of the ProASIC3 device (the "scope" of the spine; see Figure 2-9 on page 2-10). Each spine is accessed by the dedicated global network MUX tree architecture, which defines how a particular spine is driven--either by the signal on the global network from a CCC, for example, or another net defined by the user (Figure 2-12 on page 214). Quadrant spines can be driven from user I/Os on the north and south sides of the die. The ability to drive spines in the quadrant global networks can have a significant effect on system performance for high-fanout inputs to a design. Details of the chip (main) global network spine-selection MUX are presented in Figure 2-12 on page 2-14. The spine drivers for each spine are located in the middle of the die. Quadrant spines are driven from a north or south rib. Access to the top and bottom ribs is from the corner CCC or from the I/O on the north and south sides of the device. For details on using spines in ProASIC3 devices, see the Actel application note Using Global Resources in Actel ProASIC3/E Devices.
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Quadrant Global Pads T1
T2
T3
PAD RING
High-Performance Global Network
PAD RING
I/O RING
Top Spine
Chip (main) Global Pads
Global Pads Global Spine
I/O RING
Bottom Spine
Global Ribs Scope of Spine (Shaded area plus local RAMs and I/Os) Embedded RAM Blocks
Spine-Selection MUX
PAD RING
B1
B2
B3
Logic Tiles
Figure 2-11 * Spines in a Global Clock Tree Network
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Clock Aggregation
Clock aggregation allows for multi-spine clock domains. A MUX tree provides the necessary flexibility to allow long lines or I/Os to access domains of one, two, or four global spines. Signal access to the clock aggregation system is achieved through long-line resources in the central rib, and also through local resources in the north and south ribs, allowing I/Os to directly feed into the clock system. As Figure 2-13 indicates, this access system is contiguous. There is no break in the middle of the chip for the north and south I/O VersaNet access. This is different from the quadrant clocks, located in these ribs, which only reach the middle of the rib. Refer to the Using Global Resources in Actel ProASIC3/E Devices application note.
Internal/External Signals
Internal/External Signals
Tree Node MUX
Tree Node MUX
Internal/External Signal Tree Node MUX Global Rib
Internal/External Signal Global Driver MUX
Spine
Figure 2-12 * Spine Selection MUX of Global Tree
Global Spine Global Rib Global Driver and MUX Tree Node MUX
I/O Access Internal Signal Access Global Signal Access
I/O Tiles
Figure 2-13 * Clock Aggregation Tree Architecture
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Clock Conditioning Circuits
Overview of Clock Conditioning Circuitry
In ProASIC3 devices, the clock conditioning circuits (CCCs) are used to implement frequency division, frequency multiplication, phase shifting, and delay operations. The CCCs are available in six chip locations - each of the four chip corners and in the middle of the east and west chip sides. Each CCC can implement up to three independent global buffers (with or without programmable delay), or a PLL function (programmable frequency division/ multiplication, phase shift, and delays) with up to three global outputs. Unused global outputs of a PLL can be used to implement independent global buffers, up to a maximum of three global outputs for a given CCC. A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, and CLKC-GLC) of a given CCC. A PLL macro uses the CLKA CCC input to drive its reference clock. It uses the GLA and optionally the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global outputs cannot be reused if the YB (or YC) outputs are used (Figure 2-14 on page 2-16). Refer to the "PLL Macro" section on page 217 for more information. Each global buffer, as well as the PLL reference clock, can be driven from one of the following: * * * Three dedicated single-ended hardwired connection I/Os using a
Global Buffers with No Programmable Delays The CLKBUF and CLKBUF_LVPECL/LVDS macros are composite macros that include an I/O macro driving a global buffer, which uses a hardwired connection. The CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are pass-through clock sources and do not use the PLL or provide any programmable delay functionality. The CLKINT macro provides a global buffer function driven by the FPGA core. Many specific CLKBUF macros support the wide variety of single-ended and differential I/O standards supported by ProASIC3 devices. The available CLKBUF macros are described in the ProASIC3/E Macro Library Guide. Global Buffer with Programmable Delay The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to delay the clock input using a programmable delay. The CLKDLY macro takes the selected clock input and adds a userdefined delay element. This macro generates an output clock phase shift from the input clock. The CLKDLY macro can be driven by an INBUF* macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards supported by the ProASIC3 family. The available INBUF macros are described in the ProASIC3/E Macro Library Guide. The CLKDLY macro can be driven directly from the FPGA core. The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired I/O connection described earlier. The visual CLKDLY configuration in the ACTgen part of the Libero IDE and Designer tools allows the user to select the desired amount of delay, and configures the delay elements appropriately. ACTgen also allows the user to select where the input clock is coming from. ACTgen will automatically instantiate the special macro, PLLINT, when needed.
Two dedicated differential I/Os using a hardwired connection The FPGA core
The CCC block is fully configurable, either via Flash configuration bits set in the programming bitstream or through an asynchronous interface. This asynchronous interface is dynamically accessible from inside the ProASIC3 device to permit parameter changes (such as divide ratios) during device operation. To increase the versatility and flexibility of the clock conditioning system, the CCC configuration is determined either by the user during the design process, with configuration data being stored in Flash memory as part of the device programming procedure, or by writing data into a dedicated shift register during normal device operation. This latter mode allows the user to dynamically reconfigure the CCC without the need for core programming. The shift register is accessed through a simple serial interface. Refer to the UJTAG Applications in ProASIC3/E Device application note and the "CCC Electrical Specifications" section on page 2-20 for more information.
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Clock Source
Input LVDS/LVPECL Macro
Clock Conditioning
PLL Macro
CLKA GLA LOCK GLB YB GLC YC
Output
GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC)
PADN PADP
Y
POWERDOWN
INBUF* Macro PAD Y
OADIV[4:0] OAMUX[2:0] DLYGLA[4:0] OBDIV[4:0] OBMUX[2:0] DLYYB[4:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYYC[4:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0]
CLKDLY Macro CLK GL
GLA or GLB
DLYGL[4:0]
or GLC
CLKBUF_LVDS/LVPECL Macro PADN PADP Y
CLKBUF Macro PAD Y
CLKINT Macro A Y
Notes: 1. Visit the Actel website for future application notes concerning dynamic PLL reconfiguration.The PLL is only supported on the west center CCC. The A3P030 has no PLL support. Refer to the "PLL Macro" section on page 2-17 for signal descriptions. 2. Refer to the ProASIC3/E Macro Library Guide for more information. 3. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards supported by the ProASIC3 family. The available INBUF macros are described in the ProASIC3/E Macro Library Guide. Figure 2-14 * ProASIC3 CCC Options
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ProASIC3 Flash Family FPGAs
PLL Macro1 The PLL functionality of the clock conditioning block is supported by the PLL macro. Note that the PLL macro reference clock uses the CLKA input of the CCC block, which is only accessible from the global A[0:2] package pins. Refer to Figure 2-15 on page 2-18 for more information. The PLL macro provides five derived clocks (three independent) from a single reference clock. The PLL macro also provides power-down input and lock output signals. See Figure 2-17 on page 2-19 for more information. Inputs: * CLKA: selected clock input * Powerdown (active low): disables PLLs. The default state is Powerdown On (active low). Outputs: * Lock: indicates that PLL output has locked on the input reference signal * GLA, GLB, GLC: outputs to respective global networks * YB, YC: allows output from the CCC to be routed back to the FPGA core As previously described, the PLL allows up to five flexible and independently-configurable clock outputs. Figure 2-19 on page 2-21 illustrates the various clock output options and delay elements. As illustrated, the PLL supports three distinct output frequencies from a given input clock. Two of these (GLB and GLC) can be routed to the B and C global network access, respectively, and/or routed to the device core (YB and YC).
There are five delay elements to support phase control on all five outputs (GLA, GLB, GLC, YB, and YC). There is also a delay element in the feedback loop that can be used to advance the clock relative to the reference clock. The PLL macro reference clock can be driven by an INBUF* macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. The PLL macro reference clock can be driven by an INBUF* macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. The PLL macro reference clock can be driven directly from the FPGA core. The PLL macro reference clock can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired I/O connection described earlier. The visual PLL configuration in ACTgen, associated with the Libero IDE and Designer tools, will derive the necessary internal divider ratios based on the input frequency and desired output frequencies selected by the user. ACTgen also allows the user to select the various delays and phase shift values necessary to adjust the phases between the reference clock (CLKA) and the derived clocks (GLA, GLB, GLC, YB and YC). ACTgen also allows the user to select where the input clock is coming from. ACTgen automatically instantiates the special macro, PLLINT, when needed.
1. The A3P030 device does not support PLL.
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ProASIC3 Flash Family FPGAs
Each shaded box represents an input buffer called out by the appropriate INBUF or INBUF_LVDS/LVPECL. Sample Pin Names GAA0/IO0NDB0V0
1
To Core
GAA1/IO00PDB0V0
1
+
Source for CCC (CLKA or CLKB or CLKC)
GAA2/IO13PDB7V1
1
+
Routed Clock 2 (from FPGA Core)
GAA[0:2]: GA represents global in the northwest corner of the device. A[0:2]: designates specific A clock source.
Notes: 1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric. Refer to the "User I/O Naming Convention" on page 2-46 for more information. 2. Instantiate the routed clock source input as follows: a) Connect the output of a logic element to the clock input of PLL, CLKDLY, or CLKINT macro. b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location. 3. LVDS-based clock sources are only available on A3P250 through A3P1000 family members. A3P060 and A3P125 only support singleended clock sources. The A3P030 device does not support this feature. Figure 2-15 * Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT
CLKBUF PAD Y
CLKINT A Y
CLKBUF_LVDS/LVPECL PADN PADP
Note: The A3P030 device does not support this feature. Figure 2-16 * CLKBUF and CLKINT
Y
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Table 2-3 * Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros CLKBUF Macros CLKBUF_LVCMOS5 CLKBUF_LVCMOS33* CLKBUF_LVCMOS18 CLKBUF_LVCMOS15 CLKBUF_PCI CLKBUF_LVDS CLKBUF_LVPECL Note: *By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology. For more details refer to the ProASIC3/E Macro Library Guide.
CLKDLY
CLK GL
DLYGL[4:0]
Note: The CLKDLY macro uses programmable delay element type 2. Figure 2-18 * CLKDLY
CLKA POWERDOWN
GLA GLB YB GLC YC LOCK
OADIV[4:0]* OAMUX[2:0]* DLYGLA[4:0]* OBDIV[4:0]* OBMUX[2:0]* DLYYB[4:0]* DLYGLB[4:0]* OCDIV[4:0]* OCMUX[2:0]* DLYYC[4:0]* DLYGLC[4:0]* FINDIV[6:0]* FBDIV[6:0]* FBDLY[4:0]* FBSEL[1:0]* XDLYSEL* VCOSEL[2:0]*
Note: *Visit the Actel website for future application notes concerning the dynamic PLL. The A3P030 device does not support PLL. Figure 2-17 * CCC/PLL Macro
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ProASIC3 Flash Family FPGAs
CCC Electrical Specifications
Timing Characteristics
Table 2-4 * ProASIC3 CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks
1, 2
Min. 1.5 0.75
Typ.
Max. 350 350
Unit MHz MHz ps
160 32 1.5 Max Peak-to-Peak Period Jitter 1 Global Network Used 3 Global Networks Used 0.70% 1.20% 2.00% 5.60% 150 48.5 0.6 0.025 2.2 51.5 5.56 5.56
Number of Programmable Values in Each Programmable Delay Block Input Period Jitter CCC Output Peak-to-Peak Period Jitter FCCC_OUT
ns
0.75 MHz to 24 MHz 24 MHz to 100 MHz 100 MHz to 250 MHz 250 MHz to 350 MHz Acquisition Time Output Duty Cycle Delay Range in Block: Programmable Delay 1 1, 2 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay Notes:
1, 2 1, 2
0.50% 1.00% 1.75% 2.50%
s % ns ns ns
1. This delay is a function of voltage and temperature. See Table 3-6 on page 3-4 for deratings. 2. TJ = 25C, VCC = 1.5 V 3. The A3P030 device does not support PLL.
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CCC Physical Implementation2
The CCC circuit is composed of the following (Figure 2-19): * * * * PLL core Three phase selectors Six programmable delays and one fixed delay that advance/delay phase Five programmable frequency dividers that provide frequency multiplication/division (not shown in Figure 2-19, because they are automatically configured based on the user's required frequencies) One dynamic shift register that provides CCC dynamic reconfiguration capability
CCC Programming
The clock conditioning circuit block is fully configurable, either via static Flash configuration bits in the array, set by the user in the programming bitstream, or through an asynchronous dedicated shift register dynamically accessible from inside the ProASIC3 device. The dedicated shift register permits parameter changes such as PLL divide ratios and delays during device operation. This latter mode allows the user to dynamically reconfigure the PLL without the need for core programming. The register file is accessed through a simple serial interface. Refer to the UJTAG Applications in ProASIC3/E Devices application note for more information.
*
CLKA Four-Phase Output PLL Core Phase Select Programmable Delay Type 2 GLA
Fixed Delay
Programmable Delay Type 1 Phase Select Programmable Delay Type 2 Programmable Delay Type 1 Programmable Delay Type 2 GLB
YB GLC
Clock divider and clock multiplier blocks are not shown in this figure or in ACTgen. They are automatically configured based on the user's required frequencies.
Phase Select
Programmable Delay Type 1
YC
Note: Refer to the "Clock Conditioning Circuits" section on page 2-15 and Table 2-4 on page 2-20 for signal descriptions. Figure 2-19 * PLL Block
2. The A3P030 device does not support PLL.
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ProASIC3 Flash Family FPGAs
Nonvolatile Memory (NVM)
Overview of User Nonvolatile FlashROM (FROM)
ProASIC3 devices have 1 kbit of on-chip nonvolatile Flash memory that can be read from the FPGA core fabric. The FROM is arranged in 8 banks of 128 bits during programming. The 128 bits in each bank are addressable as 16 bytes during the read back of the FROM from the FPGA core (Figure 2-20). The FROM can only be programmed via the IEEE1532 JTAG port. It cannot be programmed directly from the FPGA core. When programming, each of the 8 128-bit banks can be selectively reprogrammed. The FROM can only be reprogrammed on a bank boundary. Programming involves an automatic, on-chip bank erase prior to reprogramming the bank. The FROM supports asynchronous read with a nominal 10 ns access time. The FROM can be read on byte boundaries. The upper 3 bits of the FROM address from the FPGA core define the bank that is being accessed. The lower 4 bits of the FROM address from the FPGA core define which of the 16 bytes in the bank is being accessed.
Byte Number in Bank
15 14 13 12 11 10 9
4 LSB of ADDR (READ)
8 7
6
5
4
3
2
1
0
Figure 2-20 * FROM Architecture
Bank Number 3 MSB of ADDR (READ)
7 6 5 4 3 2
1
0
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SRAM and FIFO3
ProASIC3 devices have embedded SRAM blocks along the north side of the device. In addition, A3P600 and A3P100 have an embedded SRAM block on the south side of the device. To meet the needs of high-performance designs, the memory blocks operate strictly in synchronous mode for both read and write operations. The read and write clocks are completely independent, and each may operate at any desired frequency less than or equal to 350 MHz. * * * 4kx1, 2kx2, 1kx4, 512x9 (dual-port RAM - two read, two write or one read, one write) 512x9, 256x18 (two-port RAM - one read and one write) Sync write, sync pipelined / nonpipelined read The ProASIC3 architecture enables the read and write sizes of RAMs to be organized independently, allowing for bus conversion. For example, the write side size can be set to 256x18 and the read size to 512x9. Both the write width and read width for the RAM blocks can be specified independently with the WW (write width) and RW (read width) pins. The different DxW configurations are: 256x18, 512x9, 1kx4, 2kx2, and 4kx1. Refer to the allowable RW and WW values supported for each of the RAM macro types in Table 2-5 on page 2-26. When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. The RAM blocks employ little-endian byte order for read and write operations.
The ProASIC3 memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (Full, Empty, AFULL, AEMPTY). Block diagrams of the memory modules are illustrated in Figure 2-21 on page 2-24. During RAM operation, addresses are sourced by the user logic and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. Refer to Figure 2-22 on page 2-25 for more information about the implementation of the embedded FIFO controller.
3. The A3P030 device does not support SRAM and FIFO.
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ProASIC3 Flash Family FPGAs
RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0
RAM512x18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP
FIFO4K18 RD17 RD16
RD0 FULL AFULL EMPTY AEMPTY
DINA0
RW1 RW0
AEVAL11 AEVAL10
WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0
PIPE
AEVAL0 AFVAL11 AFVAL10
REN RCLK WADDR8 WADDR7
AFVAL0 REN RBLK RCLK WD17 WD16
WADDR0 WD17 WD16
WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0 WD0 WEN WBLK WCLK RPIPE
WEN WCLK RESET
RESET
Note: The A3P030 device does not support SRAM and FIFO. Figure 2-21 * Supported Basic RAM Macros
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WD RCLK WCLK
FREN
FWEN
CNT 12
RBLK REN ESTOP
E
= AFVAL
FULL AFULL AEMPTY
WBLK WEN FSTOP Reset
CNT 12
SUB 12
AEVAL
E
=
EMPTY
Note: The A3P030 device does not support SRAM and FIFO. Figure 2-22 * ProASIC3 RAM Block with Embedded FIFO Controller
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RW[2:0] WW[2:0]
RPIPE
RD [17:0] WD [17:0] RCLK WCLK RAM RADD [J:0] WADD [J:0] REN WEN
RD
2-25
ProASIC3 Flash Family FPGAs
Signal Descriptions for RAM4K94
The following signals are used to configure the RAM4K9 memory element:
RESET This active low signal resets the output to zero when asserted. It does not reset the contents of the memory. ADDRA and ADDRB These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4k is specified, the unused high-order bits must be grounded (Table 2-6).
Table 2-6 * Address Pins Unused/Used for Various Supported Bus Widths ADDRx DxW 4kx1 2kx2 1kx4 512x9 Unused None [11] [11:10] [11:9] Used [11:0] [10:0] [9:0] [8:0]
WIDTHA and WIDTHB These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 2-5).
Table 2-5 * Allowable Aspect Ratio Settings for WIDTHA[1:0] WIDTHA1, WIDTHA0 00 01 10 11 WIDTHB1, WIDTHB0 00 01 10 11 DxW 4kx1 2kx2 1kx4 512x9
Note: The aspect ratio settings are constant and cannot be changed on-the-fly.
BLKA and BLKB These signals are active low and will enable the respective ports when asserted. When a BLKx signal is deasserted, that port's outputs hold the previous value. WENA and WENB These signals switch the RAM between read and write modes for the respective ports. A Low on these signals indicates a write operation, and a High indicates a read. CLKA and CLKB These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. PIPEA and PIPEB These signals are used to specify pipelined read on the output. A Low on PIPEA and/or PIPEB indicates a nonpipelined read and the data appears on the corresponding output in the same clock cycle. A High indicates a pipelined read and data appears on the corresponding output in the next clock cycle. WMODEA and WMODEB These signals are used to configure the behavior of the output when RAM is in the write mode. A Low on these signals makes the output retain data from the previous read. A High indicates pass-through behavior where the data being written will appear immediately on the output. This signal is overridden when the RAM is being read.
Note: The "x" in ADDRx implies A or B.
DINA and DINB These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all configurations. When a data width less than nine is specified, unused high-order signals must be grounded (Table 2-7). DOUTA and DOUTB These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with DINA and DINB, high-order bits may not be used (Table 2-7). The output data on unused pins is undefined.
Table 2-7 * Unused/Used Input and Output Data Pins for Various Supported Bus Widths DINx/DOUTx DxW 4kx1 2kx2 1kx4 512x9 Unused [8:1] [8:2] [8:4] None Used [0] [1:0] [3:0] [8:0]
Note: The "x" in DINx or DOUTx implies A or B.
4. The A3P030 device does not support SRAM and FIFO.
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ProASIC3 Flash Family FPGAs
Signal Descriptions for RAM512X185
RAM512X18 has slightly different behavior than the RAM4K9, as it has dedicated read and write ports. ProASIC3 devices support inversion (bubble pushing) throughout the FPGA architecture, including the clock input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic or in the HDL code will be automatically accounted for during design compile without incurring additional delay in the clock path. The two-port SRAM can be clocked on the rising edge or falling edge of the WCLK and RCLK. If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion management (bubble pushing) is automatically used within the ProASIC3 development tools, without performance penalty.
WW and RW These signals enable the RAM to be configured in one of the two allowable aspect ratios (Table 2-8).
Table 2-8 * Aspect Ratio Settings for WW[1:0] WW1, WW0 01 10 00, 11 RW1, RW0 01 10 00, 11 DxW 512x9 256x18 Reserved
WD and RD These are the input and output data signals, and they are 18 bits wide. When a 512x9 aspect ratio is used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read, then RD[17:9] are undefined. WADDR and RADDR These are read and write addresses, and they are nine bits wide. When the 256x18 aspect ratio is used for write and/or read, WADDR[8] and/or RADDR[8] are/is unused and must be grounded. WCLK and RCLK These signals are the write and read clocks, respectively. They are both active high. WEN and REN These signals are the write and read enables, respectively. They are both active low by default. These signals can be configured as active high. RESET This active low signal resets the output to zero when asserted. It does not reset the contents of the memory. PIPE This signal is used to specify pipelined read on the output. A Low on PIPE indicates a nonpipelined read and the data appears on the output in the same clock cycle. A High indicates a pipelined read and data appears on the output in the next clock cycle. Clocking The dual-port SRAM blocks are only clocked on the rising edge. ACTgen allows falling-edge triggered clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are clocked on either edge (rising or falling). For dual-port SRAM, each port can be clocked on either edge and/or by separate clocks by port.
Modes of Operation There are two read modes and one write mode: * Read Nonpipelined (synchronous - one clock edge): In the standard read mode, new data is driven onto the RD bus in the same clock cycle following RA and REN valid. The read address is registered on the read port clock active edge and data appears at RD after the RAM access time. Setting PIPE to OFF enables this mode. * Read Pipelined (synchronous - two clock edges): The pipelined mode incurs an additional clock delay from the address to the data but enables operation at a much higher frequency. The read address is registered on the read port active clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting the PIPE to ON enables this mode. * Write (synchronous - one clock edge): On the write clock active edge, the write data is written into the SRAM at the write address when WEN is high. The setup times of the write address, write enables, and write data are minimal with respect to the write clock. Write and read transfers are described with timing requirements in the "DDR Module Specifications" section on page 3-37. RAM Initialization Each SRAM block can be individually initialized on power-up by means of the JTAG port using the UJTAG mechanism (refer to the "JTAG 1532" section on page 251 and the ProASIC3/E SRAM/FIFO Blocks application note). The shift register for a target block can be selected and loaded with the proper bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single operation.
5. The A3P030 device does not support SRAM and FIFO.
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ProASIC3 Flash Family FPGAs
Signal Descriptions for FIFO4K186
The following signals are used to configure the FIFO4K18 memory element:
18. The output data on unused pins is undefined (Table 2-10).
Table 2-10 * Input Data Signal Usage for Different Aspect Ratios DxW 4kx1 2kx2 1kx4 512x9 256x18 WD/RD Unused WD[17:1], RD[17:1] WD[17:2], RD[17:2] WD[17:4], RD[17:4] WD[17:9], RD[17:9] -
WW and RW These signals enable the FIFO to be configured in one of the five allowable aspect ratios (Table 2-9).
Table 2-9 * Aspect Ratio Settings for WW[2:0] WW2, WW1, WW0 000 001 010 011 100 101, 110, 111 RW2, RW1, RW0 000 001 010 011 100 101, 110, 111 DxW 4kx1 2kx2 1kx4 512x9 256x18 Reserved
WBLK and RBLK These signals are active low and will enable the respective ports when low. When the RBLK signal is high, that port's outputs hold the previous value. WEN and REN Read and write enables. WEN is active low and REN is active high by default. These signals can be configured as active high or low. WCLK and RCLK These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. RPIPE This signal is used to specify pipelined read on the output. A Low on RPIPE indicates a nonpipelined read and the data appears on the output in the same clock cycle. A High indicates a pipelined read and data appears on the output in the next clock cycle. RESET This active low signal resets the output to zero when asserted. It resets the FIFO counters. It also sets all the RD pins low, the Full and AFULL pins low, and the Empty and AEMPTY pins high (Table 2-10). WD This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data width less than 18 is specified, unused higher-order signals must be grounded (Table 2-10). RD This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD bus, highorder bits become unusable if the data width is less than
6. The A3P030 device does not support SRAM and FIFO.
ESTOP, FSTOP ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the Empty flag goes high). A High on this signal inhibits the counting. FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e., the Full flag goes high). A High on this signal inhibits the counting. For more information on these signals, refer to the "ESTOP and FSTOP Usage" section. FULL, EMPTY When the FIFO is full and no more data can be written, the Full flag asserts high. The Full flag is synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to prevent overflows. Since the write address is compared to a resynchronized (and thus timedelayed) version of the read address, the Full flag will remain asserted until two WCLK active edges after a read operation eliminates the full condition. When the FIFO is empty and no more data can be read, the Empty flag asserts high. The Empty flag is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition and to prevent underflows. Since the read address is compared to a resynchronized (and thus time delayed) version of the write address, the Empty flag will remain asserted until two RCLK active edges, after a write operation, removes the empty condition. For more information on these signals, refer to the "FIFO Flag Usage Considerations" section on page 2-29. AFULL, AEMPTY These are programmable flags and will be asserted on the threshold specified by AFVAL and AEVAL, respectively. When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading, the AEMPTY output will go high. Likewise, when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output will go high.
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AFVAL, AEVAL The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold values, respectively. They are 12-bit signals. For more information on these signals, refer to the "FIFO Flag Usage Considerations" section. ESTOP and FSTOP Usage The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty (i.e., the EMPTY flag goes high). Likewise, the FSTOP pin is used to stop the write counter from counting any further once the FIFO is full (i.e., the Full flag goes high). The FIFO counters in the ProASIC3 device start the count at 0, reach the maximum depth for the configuration (e.g., 511 for a 512x9 configuration), and then restart at 0. An example application for the ESTOP, where the read counter keeps counting, would be writing to the FIFO once and reading the same content over and over without doing another write. FIFO Flag Usage Considerations The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values, respectively. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR) counters. WADDR is incremented every time a write operation is performed, and RADDR is incremented every time a read operation is performed. Whenever the difference between WADDR and RADDR is greater than or equal to AFVAL, the AFULL output is asserted. Likewise, whenever the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is asserted. To handle different read and write aspect ratios, AFVAL and AEVAL are expressed in terms of total data bits instead of total data words. When users specify AFVAL and AEVAL in terms of read or write words, the ACTgen tool translates them into bit addresses and configures these signals automatically. ACTgen configures the AFULL flag, AFULL, to assert when the write address exceeds the read address by at least a predefined value. In a 2kx8 FIFO, for example, a value of 1,500 for AFVAL means that the AFULL flag will be asserted after a write when the difference between the write address and the read address reaches 1,500 (there have been at least 1,500 more writes than reads). It will stay asserted until the difference between the write and read addresses drops below 1,500. The AEMPTY flag is asserted when the difference between the write address and the read address is less than a predefined value. In the example above, a value of 200 for AEVAL means that the AEMPTY flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. It will stay asserted until that difference rises above 200. Note that the FIFO can be configured with different read and
write widths; In this case the AFVAL setting is based on the number of write data entries and the AEVAL setting is based on the number of read data entries. For aspect ratios of 512x9 and 256x18, only 4,096 bits can be addressed by the 12 bits of AFVAL and AEVAL, the number of words must be multiplied by 8 and 16, instead of 9 and 18. The ACTgen tool automatically uses the proper values. To avoid half-words being written or read, which could happen if different read and write aspect ratios are specified, the FIFO will assert Full or Empty as soon as at least a minimum of one word cannot be written or read. For example, if a two-bit word is written and a four-bit word is being read, FIFO will remain in the Empty state when the first word is written. This occurs even if the FIFO is not completely empty, because in this case a complete word cannot be read. The same is applicable in the Full state. If a four-bit word is written and a two-bit word is read, the FIFO is full and one word is read. The FULL flag will remain asserted because a complete word cannot be written at this point. Refer to the ProASIC3/E SRAM/FIFO Blocks application note for more information.
Advanced I/Os
Introduction
ProASIC3 devices feature a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) through a bank-selectable voltage. Table 2-11 on page 2-30, Table 2-12 on page 2-30, and Table 2-18 on page 2-44 show the voltages and the compatible I/O standards. I/Os provide programmable slew rates (except A3P030), drive strengths, weak pull-up, and weak pulldown circuits. 3.3 V PCI and 3.3 V PCI-X are 5 V tolerant. See the "5 V Input Tolerance" section on page 2-37 for possible implementations of 5 V tolerance. All I/Os are in a known state during power-up and any power-up sequence is allowed without current impact. Refer to the for more information.
I/O Tile
The ProASIC3 I/O tile provides a flexible, programmable structure for implementing a large number of I/O standards. In addition, the registers available in the I/O tile in selected I/O banks can be used to support highperformance register inputs and outputs, with register enable if desired (Figure 2-23 on page 2-32). The registers can also be used to support the JESD-79C Double Data Rate (DDR) standard within the I/O structure (see the "Double Data Rate (DDR) Support" section on page 2-33 for more information). As depicted in Figure 2-23 on page 2-32, all I/O registers share one CLR port. The output register and output enable register share one CLK port. Refer to the "I/O Registers" section on page 2-32 for more information.
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ProASIC3 Flash Family FPGAs
I/O Banks and I/O Standards Compatibility
I/Os are grouped into I/O voltage banks. There are four I/O banks on the A3P250 through A3P1000. The A3P030, A3P060, and A3P125 have two I/O banks. Each I/O voltage bank has dedicated input/output supply and ground voltages (VMV/GNDQ for input buffers and VCCI/GND for output buffers). Because of these dedicated supplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Table 2-12 shows the required voltage compatibility values for each of these voltages.
Table 2-11 * ProASIC3 Supported I/O Standards A3P030 Single-Ended LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V/1.8 V/1.5 V, LVCMOS 2.5/ 5.0 V 3.3 V PCI/3.3 V PCI-X Differential LVPECL and LVDS - - -
For more information about I/O and global assignments to I/O banks, refer to the specific pin table of the device in the "Package Pin Assignments" section on page 4-1 and the "User I/O Naming Convention" section on page 2-46. I/O standards are compatible if their VCCI and VMV values are identical. VMV and GNDQ are "quiet" input power supply pins and are not used on A3P030.
A3P060
A3P125
A3P250
A3P400
A3P600
A3P1000

-
Table 2-12 * VCCI Voltages and Compatible Standards VCCI and VMV (typical) 3.3 V 2.5 V 1.8 V 1.5 V Compatible Standards LVTTL/LVCMOS 3.3, PCI 3.3, LVPECL LVCMOS 2.5, LVCMOS 2.5/5.0, LVDS LVCMOS 1.8 LVCMOS 1.5
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Features Supported on Every I/O
Table 2-13 lists all features supported by transmitter/receiver for single-ended and differential I/Os.
Table 2-13 * I/O Features Feature Single-Ended Transmitter Features * Description Hot insertion in every mode except PCI or 5 V input tolerant (these modes use clamp diodes and do not allow hot insertion) (A3P030 only) Weak pull-up and pull-down Two slew rates (except A3P030) Skew between output buffer enable/disable time: 2 ns delay (delay on rising edge) and 0 ns delay on falling edge (see
* * *
"Selectable Skew between Output Buffer Enable/ Disable Time" on page 2-41 for more information)
* * * * Single-Ended Receiver Features * * * Differential Receiver Features (A3P250 through A3P1000) * * * Three drive strengths 5 V tolerant receiver ("5 V Input Tolerance" section on
page 2-37)
LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs ("5 V Output Tolerance" section on page 2-40) High performance (Table 2-14) Electrostatics Discharge (ESD) protection High performance (Table 2-14) Separate ground and power planes, GNDQ/VMV, for input buffers only to avoid output-induced noise in the input circuitry ESD protection High performance (Table 2-14) Separate ground and power plane, GNDQ, and VMV pins for input buffers only to avoid output-induced noise in the input circuitry Two I/Os and external resistors are used to provide a CMOSstyle LVDS or LVPECL transmitter solution Weak pull-up and pull-down Fast slew rate
CMOS-Style LVDS or LVPECL Transmitter
* * *
Table 2-14 * Maximum I/O Frequency for Single-Ended and Differential I/Os (maximum drive strength and high slew selected) Specification LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V PCI PCI-X LVDS LVPECL Performance Up To 200 MHz 250 MHz 200 MHz 130 MHz 200 MHz 200 MHz 350 MHz 350 MHz
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ProASIC3 Flash Family FPGAs
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to Figure 2-23 for a simplified representation of the I/O block. The number of input registers is selected by a set of switches (not shown in Figure 2-23) between registers to implement single or differential data transmission to and from the FPGA core. The Designer software sets these switches for the user. A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O registers combining must satisfy some rules.
I/O / Q0
1 Input Reg
2 Input Reg Y Pull-Up/Down Resistor Control
To FPGA Core
I/O / Q1
CLR/PRE 3 Input Reg
PAD
ICE
CLR/PRE
I/O / ICLK
Signal Drive Strength and Slew-Rate Control
A
E= Enable Pin
I/O / D0
4 OCE Output Reg
From FPGA Core
I/O / D1 / ICE
ICE
CLR/PRE 5 Output Reg
I/O / OCLK I/O / OE
CLR/PRE 6 Output Enable Reg CLR/PRE
OCE
I/O / CLR or I/O / PRE / OCE
Note: ProASIC3 I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-33 for more information). Figure 2-23 * I/O Block Logical Representation
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Double Data Rate (DDR) Support
ProASIC3 devices support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidths and signal integrity requirements, making it very efficient for implementing very highspeed systems. In addition, high-speed implemented using LVDS. DDR interfaces can be
Input Support for DDR The basic structure to support a DDR input is shown in Figure 2-24. Three input registers are used to capture incoming data, which is presented to the core on each rising edge of the I/O register clock. Each I/O tile on ProASIC3 devices supports DDR inputs.
Output Support for DDR The basic DDR output structure is shown in Figure 2-25 on page 2-34. New data is presented to the output every half clock cycle. Note: DDR macros and I/O registers do not require additional routing. The combiner automatically recognizes the DDR macro and pushes its registers to the I/O register area at the edge of the chip. The routing delay from the I/O registers to the I/O buffers is already taken into account in the DDR macro. Refer to the Actel application note Using DDR for ProASIC3/E Devices for more information.
Input DDR
INBUF Data
A X FF1
D
X
Out_QF (To Core)
CLK CLKBUF
B X FF2
E
X
Out_QR (To Core)
CLR INBUF
C X DDR_IN
Figure 2-24 * DDR Input Register Support in ProASIC3 Devices
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ProASIC3 Flash Family FPGAs
Data_F (From Core)
A X FF1 B Out X 0 E X X FF2 1 X OUTBUF
CLK CLKBUF C D
Data_R (From Core)
CLR INBUF
B C
X X DDR_OUT
Figure 2-25 * DDR Output Support in ProASIC3 Devices
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Hot-Swap Support
Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a powered-up system. The levels of hot-swap support and examples of related applications are described in Table 215. The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required. The A3P030 device has an I/O structure that allows the support of Level 3 and Level 4 hot swap with only two levels of staging. For boards and cards with three levels of staging, it is required that card power supplies have time to reach their final value before the I/Os are connected. Pay attention to the sizing of power supply decoupling
Table 2-15 * Levels of Hot-Swap Support Hot swapping Level 1
capacitors on the card to ensure that the power supplies are not overloaded with capacitance. Cards with three levels of staging should have the following sequence: * * * Grounds Powers I/Os and other pins
For Level 3 and Level 4 compliance with the A3P030 device, cards with two levels of staging should have the following sequence: * * Grounds Powers, I/Os, other pins
Device Example of Application with Power Card Circuitry Applied Ground Connected Cards That Contain Description to Device Bus State Connection to Bus Pins ProASIC3 Devices Cold Swap No - - -
Compliance of ProASIC3 Devices
System and card with A3P030: Compliant Actel's FPGA chip are Other ProASIC3 devices: powered down, then the Compliant if the bus card gets plugged into the switch is used to isolate system, then the power FPGA I/Os from the rest supplies are turned on for of the system. the system but not for the FPGA on the card. In PCI hot-plug A3P030: Compliant I/Os specification Reset control can but do not have to circuitry isolates the card be set to hot-insertion busses until the card mode. supplies are at their Other ProASIC3 devices: nominal operating levels Compliant and stable.
2
Hot Swap while reset
Yes
Held in reset Must be made state and maintained for 1 msec before, during, and after insertion/ removal Held idle (no Same as Level ongoing I/O 2 processes during insertion/ removal)
-
3
Hot Swap while bus idle
Yes
Must remain Board bus shared with A3P030: Compliant glitch-free card bus is "frozen," and with cards with two during power there is no toggling levels of staging. up or power activity on the bus. It is Other ProASIC3 devices: down critical that the logic Compliant with cards states set on the bus with three levels of signal do not get staging. disturbed during card insertion/removal. There is activity on the A3P030: Compliant system bus, and it is with cards with two critical that the logic levels of staging. states set on the bus Other ProASIC3 devices: signal do not get Compliant with cards disturbed during card with three levels of insertion/removal. staging.
4
Hot Swap on an active bus
Yes
Bus may have Same as Level Same as active I/O 2 Level 3 processes ongoing, but device being inserted or removed must be idle
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Cold-Sparing Support
Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically connected to the system that is in operation. This means that all input buffers of the subsystem must present very high input impedance with no power applied so as not to disturb the operating portion of the system. A3P030 device fully supports cold-sparing since the I/O clamp diode is always off (see table 2-16). For other ProASIC3 devices, due to the I/O clamp diode always being active, cold-sparing can be accomplished by either employing bus switch to isolate the device I/Os from the rest of the system, or by driving each ProASIC3 IO pin to 0 V. In designs where ProASIC3 A3P030 are expected to be cold sparing compliant after supplies are turned off, a discharge resistor, switched resistor, or discharge path needs to be provided from each power supply to ground. If the resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitor is in parallel with this resistor). The RC constant should ensure full discharge of supplies before cold-sparing functionality is required. The resistor is necessary to ensure that the power pins get discharged to ground every time there is an interruption of power supply on the device.
Table 2-16 * I/O Hot-Swap and 5 V Input Tolerance Capabilities Clamp Diode1 Other ProASIC3 Devices Yes Yes Yes Yes Yes Yes Yes
Electrostatic Discharge (ESD) Protection
ProASIC3 devices are tested per JEDEC Standard JESD22-A114-B. ProASIC3 devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all device pads against damage from ESD as well as from excessive voltage transients. Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative (N) side connected to VCCI. The second diode has its P side connected to GND, and its N side connected to the pad. During operation, these diodes are normally biased in the Off state, except when transient voltage is significantly above VCCI or below GND levels. In A3P030, the first diode is always off. On other ProASIC3 devices, the clamp diode is always on and cannot be switched off. By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 2-16 for more information about the I/O standards and the clamp diode. The second diode is always connected to the pad, regardless of the I/O configuration selected.
Hot Insertion Other ProASIC3 Devices No No No No No No No
5 V Input Tolerance2 Other ProASIC3 Devices Yes2 Yes2 Yes3 Yes3 No No No Input Buffer Output Buffer
I/O Assignment 3.3 V LVTTL/LVCMOS 3.3 V PCI, 3.3 V PCI-X LVCMOS 2.5 V
4
A3P030 No N/A No No No No
6
A3P030 Yes N/A Yes Yes Yes Yes N/A
A3P030 Yes2 N/A Yes2 Yes2 No No N/A
Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled
LVCMOS 2.5 V / 5.0 V 5 LVCMOS 1.8 V LVCMOS 1.5 V Differential, LVDS/ LVPECL Notes: 1. 2. 3. 4.
N/A
The clamp diode is always off for the A3P030 device and always active for other ProASIC3 devices. Can be implemented with an external IDT bus switch, resistor divider, or zener with resistor. Can be implemented with an external resistor and an internal clamp diode. LVCMOS 2.5 V I/O standard is supported by the A3P030 device only. In the ACTgen Cores Reference Guide, select the LVCMOS25 macro for LVCMOS 2.5 V I/O standard support for the A3P030 device. 5. LVCMOS 2.5 V / 5.0 V I/O standard is supported by all ProASIC3 devices except A3P030. In the ACTgen Cores Reference Guide, select the LVCMOS5 macro for LVCMOS2.5 V/5.0 V I/O standard for all ProASIC3 devices except A3P030. 6. Bidirectional LVDS or LVPECL buffers are not supported. I/Os can either be configured as input buffers or output buffers.
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5 V Input Tolerance
I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V, and LVCMOS 2.5 V configurations are used (see Table 2-17 on page 2-40 for more details). There are four recommended solutions (see Figure 2-26 to Figure 2-29 on page 2-40 for details of board and macro setups) to achieve 5 V receiver tolerance. All the solutions meet a common requirement of limiting the voltage at the I/O input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and any voltage above 3.6 V may cause long term gate oxide failures.
Example 1 (high speed, high current): Rtx_out_high = Rtx_out_low = 10 R1 = 36 (+/-5%), P(r1)min = 0.069 R2 = 82 (+/-5%), P(r2)min = 0.158 Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 +10) = 45.04 mA tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Example 2 (low-medium speed, medium current): Rtx_out_high = Rtx_out_low = 10 R1 = 220 (+/-5%), P(r1)min = 0.018 R2 = 390 (+/-5%), P(r2)min = 0.032 Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 +10) = 9.17 mA tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V* when the transmitter sends a logic '1'. This range of Vin_dc(rx) must be assured for any combination of transmitter supply (5 V +/- 0.5 V), transmitter output resistance, and board resistor tolerances. Temporary overshoots are allowed according to Table 3-3 on page 3-2.
Solution 1 The board-level design needs to ensure that the reflected waveform at the pad does not exceed the limits provided in Table 3-3 on page 3-2. This is a long term reliability requirement. This scheme will also work for a 3.3 V PCI / PCI-X configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the two external resistors as explained below. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Here are some examples of possible resistor values (based on a simplified simulation model with no line effects, and 10 transmitter output resistance, where Rtx_out_high = (VCCI - VOH)/ IOH, Rtx_out_low = VOL / IOL).
Solution 1
ProASIC3 I/O Input 5.5 V 3.3 V
Rext1 Rext2
Requires two board resistors, LVCMOS 3.3 V I/Os
Figure 2-26 * Solution 1
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Solution 2 The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-3 on page 3-2. This is a long-term reliability requirement. This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and zener, as shown in Figure 2-27. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 2
ProASIC3 I/O Input 5.5 V 3.3 V
Rext1 Zener 3.3 V
Requires one board resistor, one Zener 3.3 V diode, LVCMOS 3.3 V I/Os
Figure 2-27 * Solution 2
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Solution 3 The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-3 on page 3-2. This is a long-term reliability requirement. This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in Figure 2-28. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Solution 3
ProASiC3 I/O Input Bus Switch IDTQS32X23 5.5 V 3.3 V
5.5 V
Requires a bus switch on the board, LVTTL/LVCMOS 3.3 V I/Os.
Figure 2-28 * Solution 3
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Solution 4
Solution 4
ProASIC3 I/O Input 2.5 V On-Chip Clamp Diode 2.5 V
5.5 V
Rext
Requires one board resistor. Available for all I/O standards excluding 3.3 V I/O standards (not supported for A3P030 device).
Figure 2-29 * Solution 4 Table 2-17 * Comparison Table for 5 V Compliant Receiver Scheme Solution 1 2 3 4 Board Components Two resistors Resistor and Zener 3.3 V Bus switch Resistor R = 250 at TJ = 70C R = 500 at TJ = 85C R = 1000 at TJ = 100C
2
Speed Low to High1
Current Limitations Limited by transmitter's drive strength Limited by transmitter's drive strength N/A Diode current 12 mA at TJ = 70C 6 mA at TJ = 85C 3 mA at TJ = 100C
Medium High Low
Notes: 1. Speed and current consumption increase as the board resistance values decrease. 2. Resistor values ensure I/O diode long term reliability.
5 V Output Tolerance
ProASIC3 I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor would pull the I/O pad voltage beyond the 3.6 V absolute maximum value, and consequently cause damage to the I/O.
When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, ProASIC3 I/Os can directly drive signals into 5 V TTL receivers. In fact, VOL = 0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and 3.3 V LVCMOS modes exceed the VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level '1' and level '0' will be recognized correctly by 5 V TTL receivers.
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Selectable Skew between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion (disable) time.
Output Enable ENABLE (IN) (from FPGA core) MUX Skew Circuit I/O Output Buffers ENABLE (OUT)
Skew Select
Figure 2-30 * Block Diagram of Output Enable Path
ENABLE (IN)
ENABLE (OUT)
Less than 0.1 ns
Figure 2-31 * Timing Diagram (Option1: Bypasses Skew Circuit)
Less than 0.1 ns
ENABLE (IN)
ENABLE (OUT) 1.2 ns (typical) Less than 0.1 ns
Figure 2-32 * Timing Diagram (Option 2: Enables Skew Circuit)
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ProASIC3 Flash Family FPGAs
At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter
current shorts. Figure 2-33 presents an example of the skew circuit implementation in a bidirectional communication system. Figure 2-34 shows how bus contention is created, and Figure 2-32 on page 2-41 shows how it can be avoided with the skew circuit.
Transmitter 1: ProASIC3 I/O Skew or Bypass Skew Routing Delay (t1
Transmitter ENABLE/ DISABLE
Transmitter 2: Generic I/O Routing Delay (t2)
EN(r1)
EN(b1)
EN(b2)
ENABLE(t2)
ENABLE(t1) Bidirectional Data Bus
Figure 2-33 * Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using ProASIC3 Devices
EN (b1)
EN (b2) ENABLE (r1)
ENABLE (t1)
Transmitter 1: OFF
Transmitter 1: ON
Transmitter 1: OFF
ENABLE (t2)
Transmitter 2: ON
Bus Contention
Transmitter 2: OFF
Figure 2-34 * Timing Diagram (Bypasses Skew Circuit)
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EN (b1) EN (b2)
ENABLE (t1)
Transmitter 1: OFF ENABLE (t2)
Transmitter 1: ON
Transmitter 1: OFF
Transmitter 2: ON
Transmitter 2: OFF
Result: No Bus Contention
Figure 2-35 * Timing Diagram (with Skew Circuit Selected)
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ProASIC3 Flash Family FPGAs
I/O Software Support
In the ProASIC3 development software, default settings have been defined for the various I/O standards that are supported. Changes can be made to the default settings via the use of attributes; however, not all I/O attributes are applicable for all I/O standards. Table 2-18 lists the valid I/O attributes that can be manipulated by the user for each I/O standard. Single-ended I/O standards in ProASIC3 support up to five different drive strengths.
Table 2-18 * I/O Attributes vs. I/O Standard Applications SLEW (output only) OUT_DRIVE (output only) SKEW (all macros with OE)* OUT_LOAD (output only)
I/O Standards LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 2.5/5.0 V LVCMOS 1.8 V LVCMOS 1.5 V PCI (3.3 V) PCI-X (3.3 V) LVDS LVPECL
RES_PULL
COMBINE_REGISTER
Note: *Applies to all ProASIC3 devices except A3P030.
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Table 2-19 lists the default values for the above selectable I/O attributes as well as those that are preset for that I/O standard. See Table 2-21 for SLEW and OUT_DRIVE settings.
Table 2-19 * I/O Default Attributes SLEW (output only) See Table 2-21 OUT_DRIVE (output only) See Table 2-21 SKEW) (tribuf and bibuf only) Off Off Off Off Off Off Off Off Off OUT_LOAD (output only) COMBINE_REGISTER 35 pF 35 pF 35 pF 35 pF 35 pF 10 pF 10 pF 0 pF 0 pF - - - - - - - - -
I/O Standards LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 2.5/5.0 V LVCMOS 1.8 V LVCMOS 1.5 V PCI (3.3 V) PCI-X (3.3 V) LVDS LVPECL
RES_PULL None None None None None None None None None
Weak Pull-Up and Weak Pull-Down Resistors
ProASIC3 devices support optional weak pull-up and pull-down resistors per I/O pin. When the I/O is pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled-down it is connected to GND. Refer to Table 3-20 on page 3-16 for more information.
The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O standards have a high output slew rate by default. For A3P030, refer to Table 2-20; for other ProASIC3 devices, refer to Table 2-21 for more information about the slew rate and drive strength specification.
Table 2-20 * A3P030 I/O Standards--OUT_DRIVE Settings OUT_DRIVE (mA) I/O Standards LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V 2 4 - 8 - -
Slew Rate Control and Drive Strength
ProASIC3 devices support output slew rate control: high and low. The A3P030 device does not support slew rate control. The high slew rate option is recommended to minimize the propagation delay. This high-speed option may introduce noise into the system if appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of noise but adds some delays in the system. Low slew rate is recommended when bus transients are expected. Drive strength should also be selected according to the design requirements and noise immunity of the system.
Table 2-21 * Other ProASIC3 Device I/O Standards--SLEW and OUT_DRIVE Settings OUT_DRIVE (mA) I/O Standards LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V 2 4 6 - 8 - 12 - - 16 - - - High High High High Slew Low Low Low Low
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User I/O Naming Convention
Due to the comprehensive and flexible nature of ProASIC3 device user I/Os, a naming scheme is used to show the details of the I/O (Figure 2-36 and Figure 2-37 on page 2-47). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os. I/O Nomenclature = Gmn/IOuxwBy Gmn is only used for I/Os that also have CCC access - i.e., global pins. G m n u x = Global = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west middle). = Global input MUX and pin number of the associated Global location m, either A0, A1,A2, B0, B1, B2, C0, C1, or C2. Figure 2-15 on page 2-18 shows the three input pins per each clock source MUX at the CCC location m. = I/O pair number in the bank, starting at 00 from the northwest I/O bank in a clockwise direction. = P (Positive) or N (Negative) for differential pairs, or R (Regular - single-ended) for the I/Os that support singleended and voltage-referenced I/O standards only. U (Positive-LVDS only) or V (Negative-LVDS only) restrict the I/O differential pair from being selected as LVPECL pair. = D (Differential Pair), P (Pair), S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency does not meet the requirements for a true differential pair. = Bank = Bank number [0..3]. The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise direction.
w
B y
VCCIB0 GND
Vcc VCCIB0 GND
GND
CCC "A"
Vcc VCCIB0 GND
GND GNDQ VMV0 VCC Bank 0 GND VCCIB0 CCC "C" GND VCC Bank 0 VCCIB0 GND VJTAG TRST TDO VPUMP GND CCC "B" CCC "D"
VMV0 GNDQ
Bank 0
VCC GND VCCIB1
Bank 1
VCOMPLF VCCPLF GND VCC VCCIB1 GND VMV1 GNDQ GND
CCC/PLL
"F"
A3P030 A3P060 A3P125
Bank 1
CCC "E"
Bank 1
TCK TDI TMS
VMV1 GNDQ GND
Note: The A3P030 device does not support PLL (VCOMPLF and VCCPLF pins). Figure 2-36 * Naming Conventions of ProASIC3 Devices with Two I/O Banks
GND VCCIB1
VCCIB1 VCC
VCCIB1 VCC GND
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VCCIB0 GND
VCC VCCIB0 GND
GND
CCC "A"
VCC VCCIB0 GND
CCC "B"
VMV0 GNDQ
Bank 0
Vcc GND VCCIB3
GND GNDQ VMV1 VCC GND VCCIB1
Bank 3
Bank 1
VCOMPLF VCCPLF GND VCC VCCIB3 GND VMV3 GNDQ GND
CCC/PLL
"F"
A3P250 A3P400 A3P600 A3P1000
CCC "C" GND VCC VCCIB1 GND VJTAG TRST TDO VPUMP GND
Bank 3
Bank 1
CCC "E"
Bank 2
CCC "D"
TCK TDI TMS
VMV2 GNDQ GND
Figure 2-37 * Naming Conventions of ProASIC3 Devices with Four I/O Banks
GND VCCIB2
VCCIB2 VCC GND
VCCIB2 VCC
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ProASIC3 Flash Family FPGAs
Pin Descriptions
Supply Pins
GND Ground
VCOMPLF
PLL Ground7
Ground to analog PLL. Unused VCOMPLF pin should be connected to GND.
VJTAG JTAG Supply Voltage
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ Ground (quiet)
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package, and improves input signal integrity. GNDQ needs to always be connected on the board to GND.
VCC Core Supply Voltage
ProASIC3 devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies power supply and printed circuit board design. If the JTAG interface is not used nor planned to be used, the VJTAG pin together with the TRST pin could be tied to GND.
VPUMP Programming Supply Voltage
Supply voltage to the FPGA core, nominal 1.5 V.
VCCIBx I/O Supply Voltage
ProASIC3 devices support single-voltage ISP programming of the configuration Flash and FROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and 3.6 V.
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are eight I/O banks on ProASIC3 devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND.
VMVx I/O Supply Voltage (quiet)
User Pins
I/O User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. Unused I/O pins are configured as inputs with pull-up resistors. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV and VCC supplies continuously powered-up, and the device transitions from programming to operating mode, the I/Os get instantly configured to the desired user configuration.
GL Globals
Quiet supply voltage to the input buffers of each I/O bank. X is the bank number. Within the package, the VMV plane is decoupled from the simultaneous switching noise originated from the output buffer VCCI domain. This minimizes the noise transfer within the package, and improves input signal integrity. Each bank must have at least one VMV connection. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLF PLL Supply Voltage7
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits" section on page 2-15. Refer to the "User I/O Naming Convention" section on page 2-46 for a description of naming of global pins.
Supply voltage to analog PLL, nominal 1.5 V. If unused, VCCPLF should be tied to GND. Refer to the PLL application note for a complete board solution for the PLL analog power supply and ground.
7. The A3P030 device does not support this feature.
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JTAG Pins
ProASIC3 devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies power supply and printed circuit board design. If the JTAG interface is not used nor planned to be used, the VJTAG pin together with the TRST pin could be tied to GND.
TCK Test Clock
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS Test Mode Select
The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK,TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin.
TRST Boundary Scan Reset Pin
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/down resistor. If JTAG is not used, Actel recommends tying off TCK to GND or VJTAG through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 2-22 for more information.
Table 2-22 * Recommended Tie-Off Values for the TCK and TRST Pins VJTAG VJTAG at 3.3 V VJTAG at 2.5 V VJTAG at 1.8 V VJTAG at 1.5 V Notes: 1. Equivalent parallel resistance if more than one device is on JTAG chain. 2. The TCK pin can be pulled-up/down. 3. The TRST pin can only be pulled-down. Tie Off Resistance2, 3 200 to 1 k 200 to 1 k 500 to 1 k 500 to 1 k
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-down resistor could be included to ensure the TAP is held in reset mode. The resistor values must be chosen from Table 2-22 and must satisfy the parallel resistance value requirement. The values in Table 2-22 correspond to the resistor recommended when a single device is used and to the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications an upset in the JTAG circuit could allow entering an undesired JTAG state. In such cases, Actel recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
Special Function Pins
NC No Connect
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
DC Don't Connect
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements.
TDI Test Data Input
This pin should not be connected to any signals on the printed circuit board (PCB). These pins should be left unconnected.
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin.
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ProASIC3 Flash Family FPGAs
Software Tools
Overview of Tools Flow
The ProASIC3 family of FPGAs is fully supported by both Actel Libero IDE and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE flow diagram located on the Actel website). Libero IDE includes Synplify(R) AE from Synplicity(R), ViewDraw(R) AE from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM AE from SynaptiCAD(R), PALACETM AE Physical Synthesis from Magma Design AutomationTM, and Designer software from Actel. Actel Designer software is a place-and-route tool and provides a comprehensive suite of back-end support tools for FPGA development. The Designer software includes the following: * Timer - a world-class integrated static timing analyzer and constraints editor that supports timing-driven place-and-route * NetlistViewer - a design netlist schematic viewer * ChipPlanner - a graphical floorplanner viewer and editor * SmartPower - tool which enables the designer to quickly estimate the power consumption of a design * PinEditor - a graphical application for editing pin assignments and I/O attributes * I/O Attribute Editor - tool which displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Actel back-annotation flow is compatible with all the major simulators. Another tool included in the Designer software is the ACTgen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence(R). The Designer software is available for both the Windows(R) and UNIX operating systems.
8. The A3P030 device does not support AES decryption.
Programming
Programming can be performed using various programming tools, such as Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Actel). The user can generate *.stp programming files from the Designer software and can use these files to program a device. ProASIC3 devices can be programmed in system. For more information on ISP of ProASIC3 devices, refer to the In-System Programming (ISP) in ProASIC3/E Using FlashPro3 and Programming a ProASIC3/E Using a Microprocessor application notes.
Security
ProASIC3 devices have a built-in 128-bit AES decryption core (except the A3P030 device). The decryption core facilitates secure, in-system programming of the FPGA core array fabric and the FROM. The FROM and the FPGA core fabric can be programmed independently from each other, allowing the FROM to be updated without the need for change to the FPGA core fabric. The AES master key is stored in on-chip nonvolatile memory (Flash). The AES master key can be preloaded into parts in a secure programming environment (such as the Actel in-house programming center) and then "blank" parts can be shipped to an untrusted programming or manufacturing center for final personalization with an AES encrypted bitstream. Late stage product changes or personalization can be implemented easily and securely by simply sending a STAPL file with AES encrypted data. Secure remote field updates over public networks (such as the Internet) are possible by sending and programming a STAPL file with AES encrypted data.
128-Bit AES Decryption8
The 128-bit AES standard (FIPS-192) block cipher is the NIST (National Institute of Standards and Technology) replacement for the DES (Data Encryption Standard FIPS46-2). AES has been designed to protect sensitive government information well into the 21st century. It replaces the aging DES, which NIST adopted in 1977 as a Federal Information Processing Standard used by federal agencies to protect sensitive, unclassified information. The 128-bit AES standard has 3.4x1038 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text using exhaustive techniques. Keys are stored (securely) in ProASIC3 devices in nonvolatile Flash memory. All programming files sent to the device can be authenticated by the part prior to programming to
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ensure that bad programming data is not loaded into the part that may possibly damage it. All programming verification is performed on-chip, ensuring that the contents of ProASIC3 devices remain secure. ARM7-ready ProASIC3 devices do not support the AES decryption capability. AES decryption can also be used on the 1,024-bit FROM to allow for secure remote updates of the FROM contents. This allows for easy, secure support for subscription model products. See the application note, ProASIC3/E Security, for more details.
ISP
ProASIC3 devices support IEEE1532 ISP via JTAG and require a single VPUMP voltage of 3.3 V during programming. In addition, programming via a Microcontroller (MCU) in a target system can be achieved. See the application note In-System Programming (ISP) in ProASIC3/E Using FlashPro3 for more details.
Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI, and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins" section on page 2-49 for pull-up/down recommendations for TDO and TCK pins. The TAP controller is a 4-bit state machine (16 states) that operates as shown in Figure 2-38 on page 2-52. The 1s and 0s represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state.
Table 2-23 * TRST and TCK Pull-Down Recommendations VJTAG VJTAG at 3.3 V VJTAG at 2.5 V VJTAG at 1.8 V VJTAG at 1.5 V Tie-off Resistance* 200 to 1 k 200 to 1 k 500 to 1 k 500 to 1 k
JTAG 1532
Programming
ProASIC3 devices support the JTAG-based IEEE1532 standard for ISP. As part of this support, when a ProASIC3 device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by keeping the global IO_EN signal deactivated, which also has the effect of disabling the input buffers. Consequently, the SAMPLE instruction will have no effect while the ProASIC3 device is in this unprogrammed state--different behavior from that of the ProASICPLUS device family. This is done because SAMPLE is defined in the IEEE1532 specification as a noninvasive instruction. If the input buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be a noninvasive instruction. Refer to the standard or the In-System Programming (ISP) in ProASIC3/E Using FlashPro3 application note for more details. For JTAG timing information of setup, hold, and fall times refer to the FlashPro User's Guide.
Note: *Equivalent parallel resistance if more than one device is on JTAG chain.
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. ProASIC3 devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary scan register cells, each with a serial-in, serialout, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary scan register cells in a device into a boundary scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O.
Boundary Scan
ProASIC3 devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. The basic ProASIC3 boundary scan logic circuit is composed of the TAP (test access port) controller, test data registers, and instruction register (Figure 2-38 on page 2-52). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-24 on page 2-52).
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ProASIC3 Flash Family FPGAs
I/O
I/O
I/O
I/O
I/O Test Data Registers
TDI
TCK
TMS
TAP Controller
Instruction Register
Device Logic
TRST
TDO
I/O
I/O
I/O
I/O
I/O
Figure 2-38 * Boundary Scan Chain in ProASIC3 Table 2-24 * Boundary Scan Opcodes Hex Opcode EXTEST HIGHZ USERCODE SAMPLE/PRELOAD IDCODE CLAMP BYPASS 00 07 0E 01 0F 05 FF
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I/O
I/O
I/O
Bypass Register
ProASIC3 Flash Family FPGAs
DC and Switching Characteristics
General Specifications
DC and switching characteristics for -F speed grade targets are based only on simulation. The characteristics provided for -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in the Table 3-1 may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating ranges specified in Table 3-2 on page 3-2.
Table 3-1 * Symbol VCC VJTAG VPUMP VCCPLL VCCI VMV VI Absolute Maximum Ratings Parameter DC core supply voltage JTAG DC voltage Programming voltage Analog power supply (PLL) DC I/O output buffer supply voltage DC I/O input buffer supply voltage I/O input voltage Limits -0.3 to 1.65 -0.3 to 3.75 -0.3 to 3.75 -0.3 to 1.65 -0.3 to 3.75 -0.3 to 3.75 -0.3 V to 3.6 V (when I/O hot insertion mode is enabled) -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) Notes: 1. Device performance is not guaranteed if storage temperature exceeds 110C. 2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 3-3 on page 3-2. Units V V V V V V V
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Table 3-2 * Symbol Ta VCC VJTAG VPUMP
Recommended Operating Conditions Parameter Ambient temperature 1.5 V DC core supply voltage JTAG DC voltage Programming voltage Programming Mode Operation3 Commercial 0 to +70 1.425 to 1.575 1.4 to 3.6 3.0 to 3.6 0 to 3.6 1.4 to 1.6 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 Industrial -40 to +85 1.425 to 1.575 1.4 to 3.6 3.0 to 3.6 0 to 3.6 1.4 to 1.6 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 Units C V V V V V V V V V V V
VCCPLL VCCI and VMV
Analog power supply (PLL) 1.5 V DC supply voltage 1.8 V DC supply voltage 2.5 V DC supply voltage 3.3 V DC supply voltage LVDS differential I/O LVPECL differential I/O
Notes: 1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 3-13 on page 3-14. VMV and VCCI should be at the same voltage within a given I/O bank. 2. All parameters representing voltages are measured with respect to GND unless otherwise specified. 3. VPUMP can be left floating during operation (not programming mode). Table 3-3 * Overshoot and Undershoot Limits (as measured on quiet I/Os)1 Average VCCI-GND Overshoot or Undershoot Duration as Percentage of Clock Cycle2 10% 5% 3V 10% 5% 3.3 V 10% 5% 3.6 V 10% 5% Notes: 1. Based on reliability requirements at 85C. 2. The duration is allowed at one cycle out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at one out of two cycles, then the maximum overshoot/undershoot has to be reduced by 0.15 V. Table 3-4 * Product Grade Commercial Industrial Flash Programming, Storage, and Operating Limits Program Retention 20 years 20 years Storage Temperature Min. 0 -40 Max. 110 110 Maximum Operating Junction Temperature TJ (C) 110 110 Maximum Overshoot/ Undershoot2 1.4 V 1.49 V 1.1 V 1.19 V 0.79 V 0.88 V 0.45 V 0.54 V
VCCI and VMV 2.7 V or less
Programming Cycles 500 500
Note: This is a stress rating only. Functional operation at any other condition other than those indicated is not implied.
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I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power-up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 3-1. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 3-1). 2. VCCI > VCC - 0.75 V (Typical). 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC = VCCI + VT Where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF
Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc.
VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: * * During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.
Internal Power-Up Activation Sequence
1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation.
VCC = 1.425 V
Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification.
Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V
Region 1: I/O buffers are OFF
Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V
Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V
VCCI
Figure 3-1 *
I/O State as a Function of VCCI and VCC Voltage Levels
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ProASIC3 Flash Family FPGAs
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 3-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + Ta
EQ 3-1
T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 3-5. P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 110C. EQ 3-2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and still air.
Where Ta = Ambient Temperature
150C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = -------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 3.90 W 20.5C/W ja (C/W) EQ 3-2 Table 3-5 * Package Thermal Resistivities ja Package Type Quad Flat No Lead (QFN) Very Thin Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Package (PQFP) Plastic Quad Flat Package (PQFP) with embedded heat spreader Fine Pitch Ball Grid Array (FBGA) Pin Count 132 100 144 208 208 144 256 484 jc 13.2 10.0 11.0 8.0 3.8 3.8 3.8 3.2 Still Air 28.9 35.3 33.5 26.1 16.2 26.9 26.6 20.5 200 ft./min. 500 ft./min. 24.6 29.4 28.0 22.5 13.3 22.9 22.8 17.0 23.1 27.1 25.7 20.8 11.9 21.5 21.5 15.9 Units C/W C/W C/W C/W C/W C/W C/W C/W
Temperature and Voltage Derating Factors
Table 3-6 * Temperature and Voltage Derating Factors for Timing Delays (Normalized to TJ = 70C, VCC = 1.425 V) Junction Temperature (C) -40C 0.88 0.83 0.80 0C 0.93 0.87 0.84 25C 0.95 0.89 0.86 70C 1.00 0.94 0.91 85C 1.02 0.96 0.92 110C 1.05 0.98 0.95
Array Voltage VCC (V) 1.425 1.500 1.575
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Calculating Power Dissipation
Quiescent Supply Current
Table 3-7 * Quiescent Supply Current Characteristics A3P030 Typical (25C) Maximum (Commercial) Maximum (Industrial) Notes: 1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 3-8 and Table 3-9 on page 3-6. 2. -F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O leakage. 2 mA 10 mA 15 mA A3P060 2 mA 10 mA 15 mA A3P125 2 mA 10 mA 15 mA A3P250 3 mA 20 mA 30 mA A3P400 3 mA 20 mA 30 mA A3P600 5 mA 30 mA 45 mA A3P1000 8 mA 50 mA 75 mA
Power Per I/O Pin
Table 3-8 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings VMV (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 2.5 3.3 2.26 5.72 1.20 1.87 3.3 2.5 1.8 1.5 3.3 3.3 - - - - - - 16.69 5.12 2.13 1.45 18.11 18.11 Static Power PDC2 (mW)1 Dynamic Power PAC9 (W/MHz)2
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Table 3-9 *
Summary of I/O Output Buffer Power (Per Pin) - Default I/O Software Settings1 CLOAD (pF) VCCI (V) 3.3 2.5 1.8 1.5 3.3 3.3 2.5 3.3 Static Power PDC3 (mW)2 - - - - - - 7.74 19.54 Dynamic Power PAC10 (W/MHz)3 468.67 267.48 138.32 96.13 201.02 201.02 88.92 166.52
Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. - - 35 35 35 35 10 10
Power Consumption of Various Internal Resources
Table 3-10 * Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices Device Specific Dynamic Power (W/MHz) A3P250 PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13 PAC14 Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial Module Average contribution of a routing net Contribution of an I/O input pin (standard dependent) Contribution of an I/O output pin (standard dependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation First contribution of a PLL Second contribution of a PLL 100 10 1.00 0.11 0.07 0.29 0.29 0.70 See Table 3-7 on page 3-5. See Table 3-8 on page 3-5 25.00 30.00 4.00 2.00
Parameter
Definition
Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator or SmartPower tool in Libero IDE software.
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ProASIC3 Flash Family FPGAs
Power Calculation Methodology
The section below describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * * * * * * * * The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 3-11 on page 3-9 Enable rates of output buffers--guidelines are provided for typical applications in Table 3-12 on page 3-9 Read rate and write rate to the memory--guidelines are provided for typical applications in Table 3-12 on page 3-9. The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption. PDYN is the total dynamic power consumption.
Total Static Power Consumption--PSTAT PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3
NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design--guideline are provided in Table 3-11 on page 3-9. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 3-11 on page 3-9. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design.
Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5+ 1* PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 3-11 on page 3-9.
FCLK is the global clock signal frequency.
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ProASIC3 Flash Family FPGAs
Combinational Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 * PAC7*FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design. FCLK is the global clock signal frequency.
1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 3-11 on page 3-9.
Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. FCLK is the global clock signal frequency.
1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 3-11 on page 3-9.
I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency.
2 is the I/O buffer toggle rate--guidelines are provided in Table 3-11 on page 3-9.
I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate--guidelines are provided in Table 3-11 on page 3-9. 1 is the I/O buffer enable rate--guidelines are provided in Table 3-12 on page 3-9.
FCLK is the global clock signal frequency.
RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
3 the RAM enable rate for write operations--guidelines are provided in Table 3-12 on page 3-9.
PLL/CCC Contribution--PPLL PPLL = PAC13 * FCLKIN + PAC14 *FCLKOUT
FCLKIN is the input clock frequency. FCLKOUT is the output clock frequency.1
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
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ProASIC3 Flash Family FPGAs
Guidelines
Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * The average toggle rate of a shift-register is 100% because all flip-flop outputs toggle at half of the clock frequency. * The average toggle rate of an 8-bit counter is 25%: - Bit 0 (LSB) = 100% - Bit 1 = 50%
- - - -
Bit 2 ...
= 25%
Bit 7 (MSB) = 0.78125% The average toggle rate is = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.
Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%.
Table 3-11 * Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10%
1 2
Component
Table 3-12 * Enable Rate Guidelines Recommended for Power Calculation Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5%
1 2 3
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ProASIC3 Flash Family FPGAs
User I/O Characteristics
Timing Model
I/O Module (Non-Registered) Combinational Cell Y t PD = 0.54 ns t PD =0.47 ns tDP = 1.34 ns I/O Module (Non-Registered) LVTTL Output drive strength = 12 mA High slew rate Combinational Cell Y LVPECL
Combinational Cell Y t PD = 0.85 ns
Buffer
t DP = 2.64 ns
Combinational Cell I/O Module (Registered) t PY = 1.05 ns t PD = 0.49 ns LVPECL D Q Combinational Cell Y t ICLKQ = 0.63 ns t ISUD = 0.43 ns Input LVTTL Clock Register Cell t PY = 0.76 ns D I/O Module (Non-Registered) t CLKQ = 0.53 ns t SUD = 0.40 ns t PY = 1.20 ns Input LVTTL Clock t PY = 0.76 ns Q Combinational Cell Y t PD = 0.46 ns t CLKQ = 0.53 ns t SUD = 0.40 ns Register Cell D Q t PD = 0.46 ns Buffer Y
I/O Module (Non-Registered) LVTTL Output drive strength = 8 mA t DP = 3.66 ns High slew rate I/O Module (Non-Registered) LVCMOS 1.5v Output drive strength = 4 mA t DP = 3.97 ns High slew rate I/O Module (Registered) D Q LVTTL 3.3 V t DP = 2.64 ns Output drive strength = 12 mA High slew rate t OCLKQ = 0.63 ns t OSUD = 0.43 ns
LVDS
Input LVTTL Clock t PY = 0.76 ns
Figure 3-2 *
Timing Model Operating Conditions: -2 Speed, Commercial Temperature Range (TJ = 70C), Worst Case VCC = 1.425 V
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t PY t PYS PAD D Y
tDIN Q DIN CLK To array
I/O interface tPY = MAX(t PY (R), tPY (F)) tPYS = MAX(t PYS (R), tPYS (F)) tDIN= MAX(t DIN(R), tDIN (F)) VIH Vtrip Vtrip VCC 50% Y GND tPY (R) tPYS (R) tPY (F) tPYS (F) VCC 50% DIN GND tDOUT (R)
Figure 3-3 * Input Buffer Timing Model and Delays (example)
PAD
VIL
50%
50% tDOUT (F)
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ProASIC3 Flash Family FPGAs
t DOUT DQ D From Array I/O interface CLK
t DP PAD Std Load t DP = MAX(t DP(R), t DP (F)) t DOUT = MAX(t DOUT (R), t DOUT (F)) t DOUT VCC 50% VCC (F) 0V
DOUT
t DOUT (R) 50%
D
DOUT
50%
50% VOH
0V
Vtrip PAD t DP (R)
Figure 3-4 * Output Buffer Model and Delays (example)
Vtrip VOL t DP (F)
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t EOUT DQ E CLK t ZL,tZH,tHZ ,tLZ, tZLS, tZHS
EOUT DQ D CLK t EOUT = MAX(t EOUT (R), t EOUT (F)) VCC D Vcc E 50% t EOUT (R) 50% tZL PAD Vtrip VOL 50% t EOUT (F) Vcc 50% tHZ 90% VCCI 50% tZH VCCI Vtrip 10% VCCI 50% tLZ DOUT PAD
I/O interface
EOUT
VCC D VCC E 50% tEOUT (R) 50% tZLS Vtrip V
OL
50% Vcc
tEOUT (F) 50% VOH 50% tZHS Vtrip
EOUT PAD
Figure 3-5 *
Tristate Output Buffer Timing Model and Delays (example)
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ProASIC3 Flash Family FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels - Default I/O Software Settings
Table 3-13 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions Drive Strength 12 mA 12 mA 8 mA 4 mA Slew Rate High High High High VIL Min, V -0.3 -0.3 -0.3 -0.3 Max, V 0.8 0.7 0.35 * VCCI 0.30 * VCCI VIH Min, V 2 1.7 0.65 * VCCI 0.7 * VCCI Max, V 3.6 3.6 3.6 3.6 VOL Max, V 0.4 0.7 0.45 0.25 * VCCI VOH Min, V 2.4 1.7 VCCI - 0.45 0.75 * VCCI IOL mA 12 12 8 4 IOH mA 12 12 8 4
I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X
Per PCI specifications Per PCI-X specifications
Note: Currents are measured at 85C junction temperature. Table 3-14 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 IIL DC I/O Standards 3.3 V LVTTL /3.3V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes: 1. Commercial range (0C < TJ < 70C) 2. Industrial range (-40C < TJ < 85C) A 10 10 10 10 10 10 IIH A 10 10 10 10 10 10 IIL A 15 15 15 15 15 15 Industrial2 IIH A 15 15 15 15 15 15
Summary of I/O Timing Characteristics - Default I/O Software Settings
Table 3-15 * Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI Measuring Trip Point (Vtrip) 1.4 V 1.2 V 0.90 V 0.75 V 0.285 * VCCI (RR) 0.615 * VCCI (FF) 3.3 V PCI-X 0.285 * VCCI (RR) 0.615 * VCCI (FF)
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Table 3-16 * I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tHZ tZH tLZ tZL tZHS tZLS Data to Pad delay through the Output Buffer Pad to Data delay through the Input Buffer Data to Output Buffer delay through the I/O interface Enable to Output Buffer Tristate Control delay through the I/O interface Input Buffer to Data delay through the I/O interface Enable to Pad delay through the Output Buffer--high to Z Enable to Pad delay through the Output Buffer--Z to high Enable to Pad delay through the Output Buffer--low to Z Enable to Pad delay through the Output Buffer--Z to low Enable to Pad delay through the Output Buffer with delayed enable--Z to high Enable to Pad delay through the Output Buffer with delayed enable--Z to low Parameter Definition
Table 3-17 * Summary of I/O Timing Characteristics--Software Default Settings Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Capacitive Load (pF) Drive Strength (mA) External Resistor
Slew Rate
tEO UT
tDOUT
I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X LVDS LVPECL Notes:
12 mA 12 mA 8 mA 4 mA Per PCI spec Per PCI-X spec 24 mA 24 mA
High High High High High High High High
35 pF 35pF 35pF 35pF 10pF 10pF - -
- - - - 25
2
0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 0.49 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 0.49 3.32 0.03 0.91 0.32 3.12 3.32 2.64 2.53 4.79 4.99 0.49 3.97 0.03 1.07 0.32 3.62 3.97 2.79 2.54 5.29 5.64 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13
25 2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 - - 0.49 1.37 0.03 1.20 0.49 1.34 0.03 1.05 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-10 on page 3-26 for connectivity. This resistor is not required during normal operation.
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Units ns ns ns ns ns ns ns ns
3-15
tZHS
tDIN
tZH
tZLS
tDP
tPY
tHZ
tZL
tLZ
ProASIC3 Flash Family FPGAs
Detailed I/O DC Characteristics
Table 3-18 * Input Capacitance Symbol CIN CINCLK Definition Input Capacitance Input Capacitance on the clock pin Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF
Table 3-19 * I/O Output Buffer Maximum Resistances1 RPULL-DOWN Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 4 mA 8 mA 12 mA 16 mA 2.5 V LVCMOS 4 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IO H sp e c Table 3-20 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () VCCI 3.3 V 2.5 V 1.8 V 1.5 V Notes: 1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) Min. 10 k 11 k 18 k 19 k Max. 45 k 55 k 70 k 90 k R(WEAK PULL-DOWN)2 () Min. 10 k 12 k 17 k 19 k Max. 45 k 74 k 110 k 140 k Per PCI/PCI-X specification ()
2
RPULL-UP ()3 300 150 75 75 200 100 50 225 112 56 224 112 75
100 50 25 25 100 50 25 200 100 50 200 100 25
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Table 3-21 * I/O Short Currents IOSH/IOSL Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 8 mA 12 mA 16 mA 2.5 V LVCMOS 4 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 8 mA 1.5 V LCMOS 2 mA 4 mA Note: *TJ = 100C IOSH (mA)* 25 51 103 103 16 32 65 9 17 35 13 25 IOSL (mA)* 27 54 109 109 18 37 74 11 22 44 16 33
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions.
Table 3-22 * Short Current Event Duration before Failure Temperature -40C 0C 25C 70C 85C 100C 110C Table 3-23 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS LVDS/LVPECL Input Rise/Fall Time (Min.) No requirement No requirement Input Rise/fall Time (Max.) 10 ns* 10 ns* Reliability 20 years (110C) 10 years (100C) Time Before Failure > 20 years > 20 years > 20 years 5 years 2 years 6 months 3 months
Note: *The Maximum Input rise/fall time is related only to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers, when Schmitt trigger is disabled, can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/ characterization of the system to ensure that there is no excessive noise coupling into input signals.
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ProASIC3 Flash Family FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor-Transistor Logic (LVTTL) is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 3-24 * Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 4 mA 8 mA 12 mA 16 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL mA 4 8 12 16 IOH IOSL IOSH IIL A2 10 10 10 10 IIH A2 10 10 10 10
Min, V Max, V Min, V Max, V Max, V Min, V -0.3 -0.3 -0.3 -0.3 0.8 0.8 0.8 0.8 2 2 2 2 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4
mA Max, mA1 Max, mA1 4 8 12 16 27 54 109 109 25 51 103 103
Test Point Data Path 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 35 pF for tZH /tZHS /tZL /tZLS 5 pF for tHZ /tLZ
Figure 3-6 *
AC Loading
Table 3-25 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points.
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Timing Characteristics
Table 3-26 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Drive Strength (mA) 4 mA Speed Grade -F Std. -1 -2 8 mA -F Std. -1 -2 12 mA -F Std. -1 -2 16 mA -F Std. -1 -2 tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 12.32 10.26 8.72 7.66 8.74 7.27 6.19 5.43 6.70 5.58 4.75 4.17 6.70 5.58 4.75 4.17 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.22 1.02 0.86 0.76 1.22 1.02 0.86 0.76 1.22 1.02 0.86 0.76 1.22 1.02 0.86 0.76 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 12.55 10.45 8.89 7.80 8.90 7.41 6.30 5.53 6.83 5.68 4.84 4.24 6.83 5.68 4.84 4.24 tZH 10.69 8.90 7.57 6.64 7.55 6.28 5.35 4.69 5.85 4.87 4.14 3.64 5.85 4.87 4.14 3.64 tLZ 3.18 2.64 2.25 1.98 3.58 2.98 2.54 2.23 3.85 3.21 2.73 2.39 3.85 3.21 2.73 2.39 tHZ 2.95 2.46 2.09 1.83 3.65 3.04 2.59 2.27 4.10 3.42 2.91 2.55 4.10 3.42 2.91 2.55 tZLS tZHS Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15.23 13.37 12.68 11.13 10.79 9.47 9.65 8.20 7.20 9.51 7.92 6.74 5.91 9.51 7.92 6.74 5.91 9.47 8.31 8.52 7.25 6.36 8.54 7.11 6.05 5.31 8.54 7.11 6.05 5.31
11.59 10.23
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-27 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Drive Strength (mA) 4 mA Speed Grade -F Std. -1 -2 8 mA -F Std. -1 -2 12 mA -F Std. -1 -2 16 mA -F Std. -1 -2 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 9.20 7.66 6.51 5.72 5.89 4.91 4.17 3.66 4.24 3.53 3.00 2.64 4.24 3.53 3.00 2.64 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.22 1.02 0.86 0.76 1.22 1.02 0.86 0.76 1.22 1.02 0.86 0.76 1.22 1.02 0.86 0.76 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 9.37 7.80 6.63 5.82 6.00 5.00 4.25 3.73 4.32 3.60 3.06 2.69 4.32 3.60 3.06 2.69 tZH 7.91 6.59 5.60 4.92 4.89 4.07 3.46 3.04 3.39 2.82 2.40 2.11 3.39 2.82 2.40 2.11 tLZ 3.18 2.65 2.25 1.98 3.59 2.99 2.54 2.23 3.86 3.21 2.73 2.40 3.86 3.21 2.73 2.40 tHZ 3.14 2.61 2.22 1.95 3.85 3.20 2.73 2.39 4.30 3.58 3.05 2.68 4.30 3.58 3.05 2.68 tZLS 10.03 8.54 7.49 8.69 7.23 6.15 5.40 7.01 5.83 4.96 4.36 7.01 5.83 4.96 4.36 tZHS 8.82 7.51 6.59 7.57 6.31 5.36 4.71 6.08 5.06 4.30 3.78 6.08 5.06 4.30 3.78 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12.05 10.60
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ProASIC3 Flash Family FPGAs
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5 V applications. It uses a 5-V-tolerant input buffer and push-pull output buffer.
Table 3-28 * Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength 4 mA 8 mA 12 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL mA 4 8 12 IOH mA 4 8 12 IOSL IOSH IIL A2 10 10 10 IIH A2 10 10 10
Min, V Max, V Min, V Max, V Max, V Min, V -0.3 -0.3 -0.3 0.7 0.7 0.7 1.7 1.7 1.7 3.6 3.6 3.6 0.7 0.7 0.7 1.7 1.7 1.7
Max, mA1 Max, mA1 18 37 74 16 32 65
Test Point Data Path 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 35 pF for tZH /tZHS /tZL /tZLS 5 pF for tHZ /tLZ
Figure 3-7 *
AC Loading
Table 3-29 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 2.5 Measuring Point* (V) 1.2 CLOAD (pF) 35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points.
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ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-30 * 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V Drive Strength (mA) 4 mA Speed Grade -F Std. -1 -2 8 mA -F Std. -1 -2 12 mA -F Std. -1 -2 tDOUT 0.72 0.60 0.51 0.45 0.72 0.60 0.51 0.45 0.72 0.60 0.51 0.45 tDP 13.69 11.40 9.69 8.51 9.56 7.96 6.77 5.94 7.42 6.18 5.26 4.61 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.57 1.31 1.11 0.98 1.57 1.31 1.11 0.98 1.57 1.31 1.11 0.98 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 13.47 11.22 9.54 8.38 9.74 8.11 6.90 6.05 7.56 6.29 5.35 4.70 tZH 13.69 11.40 9.69 8.51 9.39 7.81 6.65 5.83 7.11 5.92 5.03 4.42 tLZ 3.22 2.68 2.28 2.00 3.66 3.05 2.59 2.28 3.97 3.30 2.81 2.47 tHZ 2.65 2.20 1.88 1.65 3.47 2.89 2.46 2.16 3.99 3.32 2.83 2.48 tZLS 16.16 13.45 11.44 10.05 12.43 10.34 8.80 7.72 10.25 8.53 7.25 6.37 tZHS 16.38 13.63 11.60 10.18 12.07 10.05 8.55 7.50 9.79 8.15 6.94 6.09 Units ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-31 * 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V Drive Strength (mA) 4 mA Speed Grade -F Std. -1 -2 8 mA -F Std. -1 -2 12 mA -F Std. -1 -2 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. tDOUT 0.79 0.66 0.56 0.49 0.72 0.60 0.51 0.45 0.79 0.66 0.56 0.49 tDP 10.41 8.66 7.37 6.47 6.21 5.17 4.39 3.86 6.21 5.17 4.39 3.86 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.57 1.31 1.11 0.98 1.57 1.31 1.11 0.98 1.57 1.31 1.11 0.98 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 9.41 7.83 6.66 5.85 6.05 5.04 4.28 3.76 6.05 5.04 4.28 3.76 tZH 10.41 8.66 7.37 6.47 6.21 5.17 4.39 3.86 6.21 5.17 4.39 3.86 tLZ 3.22 2.68 2.28 2.00 3.66 3.05 2.59 2.28 3.66 3.05 2.59 2.28 tHZ 2.77 2.30 1.96 1.72 3.60 3.00 2.55 2.24 3.60 3.00 2.55 2.24 tZLS 12.09 10.07 8.56 7.52 8.74 7.27 6.19 5.43 8.74 7.27 6.19 5.43 tZHS 13.09 10.90 9.27 8.14 8.89 7.40 6.30 5.53 8.89 7.40 6.30 5.53 Units ns ns ns ns ns ns ns ns ns ns ns ns
A d v an c ed v0 . 5
3-21
ProASIC3 Flash Family FPGAs
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.8 V applications. It uses 1.8 V input buffer and push-pull output buffer.
Table 3-32 * Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS Drive Strength 2 mA 4 mA 8 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. Min, V -0.3 -0.3 -0.3 VIL Max, V 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI VIH Min, V 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI VOL Max, V Max, V 3.6 3.6 3.6 0.45 0.45 0.45 VOH Min, V VCCI - 0.45 VCCI - 0.45 VCCI - 0.45 IOL mA 2 4 8 IOH mA 2 4 8 IOSL Max, mA1 11 22 44 IOSH Max, mA1 9 17 35 IIL IIH
A2 A2 10 10 10 10 10 10
Test Point Data Path 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 35 pF for tZH /tZHS /tZL /tZLS 5 pF for tHZ /tLZ
Figure 3-8 *
AC Loading
Table 3-33 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 1.8 Measuring Point* (V) 0.9 CLOAD (pF) 35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points.
3 -2 2
Advanced v0.5
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-34 * 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V Drive Strength (mA) 2 mA Speed Grade -F Std. -1 -2 4 mA -F Std. -1 -2 8mA -F Std. -1 -2 tDOUT 0.79 0.66 0.56 0.49 0.72 0.60 0.51 0.45 0.79 0.66 0.56 0.49 tDP 18.66 15.53 13.21 11.60 12.58 10.48 8.91 7.82 9.67 8.05 6.85 6.01 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.46 1.22 1.04 0.91 1.46 1.22 1.04 0.91 1.46 1.22 1.04 0.91 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 16.95 14.11 12.01 10.54 12.51 10.41 8.86 7.77 9.85 8.20 6.97 6.12 tZH 18.66 15.53 13.21 11.60 12.58 10.48 8.91 7.82 9.42 7.84 6.67 5.86 tLZ 3.34 2.78 2.36 2.07 3.88 3.23 2.75 2.41 4.25 3.54 3.01 2.64 tHZ 1.92 1.60 1.36 1.19 3.28 2.73 2.33 2.04 3.93 3.27 2.78 2.44 tZLS 19.64 16.35 13.91 12.21 15.19 12.65 10.76 9.44 12.53 10.43 8.88 7.79 tZHS 21.34 17.77 15.11 13.27 15.27 12.71 10.81 9.49 12.11 10.08 8.57 7.53 Units ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-35 * 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V Drive Strength (mA) 2 mA Speed Grade -F Std. -1 -2 4 mA -F Std. -1 -2 8 mA -F Std. -1 -2 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. tDOUT 0.79 0.66 0.56 0.49 0.72 0.60 0.51 0.45 0.79 0.66 0.56 0.49 tDP 14.25 11.86 10.09 8.86 8.31 6.91 5.88 5.16 5.34 4.45 3.78 3.32 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.46 1.22 1.04 0.91 1.46 1.22 1.04 0.91 1.46 1.22 1.04 0.91 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 10.97 9.14 7.77 6.82 7.04 5.86 4.99 4.38 5.02 4.18 3.56 3.12 tZH 14.25 11.86 10.09 8.86 8.31 6.91 5.88 5.16 5.34 4.45 3.78 3.32 tLZ 3.33 2.77 2.36 2.07 3.87 3.22 2.74 2.41 4.24 3.53 3.00 2.64 tHZ 1.99 1.66 1.41 1.24 3.41 2.84 2.41 2.12 4.06 3.38 2.88 2.53 tZLS 13.66 11.37 9.67 8.49 9.73 8.10 6.89 6.05 7.71 6.42 5.46 4.79 tZHS 16.94 14.10 11.99 10.53 10.99 9.15 7.78 6.83 8.03 6.68 5.69 4.99 Units ns ns ns ns ns ns ns ns ns ns ns ns
A d v an c ed v0 . 5
3-23
ProASIC3 Flash Family FPGAs
1.5 V LVCMOS (JESD8-11)
Low-voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.5 V applications. It uses 1.5 V input buffer and push-pull output buffer.
Table 3-36 * Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS Drive Strength Min, V 2 mA 4 mA Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. -0.3 -0.3 VIL Max, V 0.30 * VCCI 0.30 * VCCI VIH Min, V 0.7 * VCCI 0.7 * VCCI Max, V 3.6 3.6 VOL Max, V 0.25 * VCCI 0.25 * VCCI VOH Min, V 0.75 * VCCI 0.75 * VCCI IOL mA 2 4 IOH mA 2 4 IOSL Max, mA1 16 33 IOSH Max, mA1 13 25 IIL A2 10 10 IIH A2 10 10
Test Point Data Path 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 35 pF for tZH /tZHS /tZL /tZLS 5 pF for tHZ /tLZ
Figure 3-9 *
AC Loading
Table 3-37 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 1.5 Measuring Point* (V) 0.75 CLOAD (pF) 35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points.
3 -2 4
Advanced v0.5
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-38 * 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V Drive Strength (mA) 2 mA Speed Grade -F Std. -1 -2 4 mA -F Std. -1 -2 tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 15.35 6 12.78 10.87 9.55 12.02 10.01 8.51 7.47 tDIN 0.052 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.728 1.44 1.22 1.07 1.73 1.44 1.22 1.07 tEOUT 0.514 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 15.38 7 12.81 10.90 9.57 12.25 10.19 8.67 7.61 tZH 15.35 6 12.78 10.87 9.55 11.47 9.55 8.12 7.13 tLZ 4.081 3.40 2.89 2.54 4.50 3.75 3.19 2.80 tHZ 3.176 2.64 2.25 1.97 3.93 3.27 2.78 2.44 tZLS 18.07 3 15.05 12.80 11.24 14.93 12.43 10.57 9.28 tZHS 18.04 2 15.02 12.78 11.22 14.15 11.78 10.02 8.80 Units ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-39 * 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V Drive Strength (mA) 2 mA Speed Grade -F Std. -1 -2 4 mA -F Std. -1 -2 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 10.05 8.36 7.11 6.24 6.38 5.31 4.52 3.97 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.73 1.44 1.22 1.07 1.73 1.44 1.22 1.07 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 8.20 6.82 5.80 5.10 5.83 4.85 4.13 3.62 tZH 10.05 8.36 7.11 6.24 6.38 5.31 4.52 3.97 tLZ 4.07 3.39 2.88 2.53 4.49 3.74 3.18 2.79 tHZ 3.32 2.77 2.35 2.06 4.09 3.40 2.89 2.54 tZLS 10.88 9.06 7.71 6.76 8.51 7.09 6.03 5.29 tZHS 12.73 10.60 9.02 7.91 9.07 7.55 6.42 5.64 Units ns ns ns ns ns ns ns ns
A d v an c ed v0 . 5
3-25
ProASIC3 Flash Family FPGAs
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications.
Table 3-40 * Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X Drive Strength Per PCI specification Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. VIL VIH VOL VOH IOL mA IOH mA IOSL IOSH IIL IIH
Min, V Max, V Min, V Max, V Max, V Min, V Per PCI curves
Max, mA1 Max, mA1 A2 A2 10 10
AC loadings are defined per the PCI/PCI-X specifications for the data path; Actel loadings for enable path characterization are described in Figure 3-10.
R = 25 Test Point Data Path
R to VCCI for tDP (F) R to GND for tDP (R)
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ
Figure 3-10 * AC Loading
AC loading are defined per PCI/PCI-X specifications for the data path; Actel loading for tristate is described in Table 3-41.
Table 3-41 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 3.3 Measuring Point* (V) 0.285 * VCCI for tDP(R) 0.615 * VCCI for tDP(F) Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points. CLOAD (pF) 10
Timing Characteristics
Table 3-42 * 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Speed Grade -F Std. -1 -2 tDOUT 0.79 0.66 0.56 0.49 tDP 3.22 2.68 2.28 2.00 tDIN 0.05 0.04 0.04 0.03 tPY 1.04 0.86 0.73 0.65 tEOUT 0.51 0.43 0.36 0.32 tZL 3.28 2.73 2.32 2.04 tZH 2.34 1.95 1.66 1.46 tLZ 3.86 3.21 2.73 2.40 tHZ 4.30 3.58 3.05 2.68 tZLS 5.97 4.97 4.22 3.71 tZHS 5.03 4.19 3.56 3.13 Units ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3 -2 6
Advanced v0.5
ProASIC3 Flash Family FPGAs
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit is carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 3-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation, because the output standard specifications are different.
Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 ZO = 50 140 N 165 ZO = 50 100 N P FPGA + INBUF_LVDS
Figure 3-11 * LVDS Circuit Diagram and Board-Level Implementation Table 3-43 * Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH VI VODIFF VOCM VICM VIDIFF Notes: 1. 5% 2. Differential input voltage = 350 mV. Table 3-44 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 1.075 Input High (V) 1.325 Measuring Point* (V) Cross point Description Supply Voltage Output Low Voltage Output High Voltage Input Voltage Differential Output Voltage Output Common Mode Voltage Input Common Mode Voltage Input Differential Voltage Min. 2.375 0.9 1.25 0 250 1.125 0.05 100 350 1.25 1.25 350 Typ. 2.5 1.075 1.425 Max. 2.625 1.25 1.6 2.925 450 1.375 2.35 Units V V V V mV V V mV
Note: *Measuring point = Vtrip. See Table 3-6 on page 3-4 for a complete table of trip points.
A d v an c ed v0 . 5
3-27
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-45 * LVDS Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V Speed Grade -F Std. -1 -2 tDOUT 0.79 0.66 0.56 0.49 tDP 2.20 1.83 1.56 1.37 tDIN 0.05 0.04 0.04 0.03 tPY 1.92 1.60 1.36 1.20 Units ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3 -2 8
Advanced v0.5
ProASIC3 Flash Family FPGAs
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 3-12. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation, because the output standard specifications are different.
Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 ZO = 50 187 W N 100 ZO = 50 100 N P FPGA
+ -
INBUF_LVPECL
Figure 3-12 * LVPECL Circuit Diagram and Board-Level Implementation Table 3-46 * Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH VIL, VIH VODIFF VOCM VICM VIDIFF Description Supply Voltage Output Low Voltage Output High Voltage Input Low, Input High voltages Differential Output Voltage Output Common Mode Voltage Input Common Mode Voltage Input Differential Voltage 0.96 1.8 0 0.625 1.762 1.01 300 Min. 3.0 1.27 2.11 3.3 0.97 1.98 2.57 1.06 1.92 0 0.625 1.762 1.01 300 Max. Min. 3.3 1.43 2.28 3.6 0.97 1.98 2.57 1.30 2.13 0 0.625 1.762 1.01 300 Max. Min. 3.6 1.57 2.41 3.9 0.97 1.98 2.57 Max. Units V V V V V V V mV
Table 3-47 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 1.64 Input High (V) 1.94 Measuring Point* (V) Cross point
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-14 for a complete table of trip points.
Timing Characteristics
Table 3-48 * LVPECL Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Speed Grade -F Std. -1 -2 tDOUT 0.79 0.66 0.56 0.49 tDP 2.16 1.80 1.53 1.34 tDIN 0.05 0.04 0.04 0.03 tPY 1.69 1.40 1.19 1.05 Units ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
A d v an c ed v0 . 5
3-29
ProASIC3 Flash Family FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
Preset
L
Pad Out
D DOUT Data_out
TRIBUF
Data
PRE D Q C DFN1E1P1 E B
E
Y Core Array
F G
PRE D Q DFN1E1P1 E
INBUF INBUF
Enable
EOUT H I
CLKBUF
CLK
A J K Data Input I/O Register with: Active High Enable Active High Preset Positive Edge Triggered PRE D Q DFN1E1P1 E
CLKBUF
INBUF
INBUF
Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive Edge Triggered
Figure 3-13 * Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
3 -3 0
Advanced v0.5
D_Enable
Enable
CLK
ProASIC3 Flash Family FPGAs
Table 3-49 * Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOPRE2Q tOREMPRE tORECPRE tOECLKQ tOESUD tOEHD tOESUE tOEHE tOEPRE2Q tOEREMPRE tOERECPRE tICLKQ tISUD tIHD tISUE tIHE tIPRE2Q tIREMPRE tIRECPRE Parameter Definition Clock-to-Q of the Output Data Register Data Setup time for the Output Data Register Data Hold time for the Output Data Register Enable Setup time for the Output Data Register Enable Hold time for the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Preset removal time for the Output Data Register Asynchronous Preset Recovery time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup time for the Output Enable Register Data Hold time for the Output Enable Register Enable Setup time for the Output Enable Register Enable Hold time for the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Preset Removal time for the Output Enable Register Asynchronous Preset Recovery time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup time for the Input Data Register Data Hold time for the Input Data Register Enable Setup time for the Input Data Register Enable Hold time for the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Preset Removal time for the Input Data Register Asynchronous Preset Recovery time for the Input Data Register Measuring Nodes (From, To)* H, DOUT F, H F, H G, H G, H L, DOUT L, H L, H H, EOUT J, H J, H K, H K, H I, EOUT I, H I, H A, E C, A C, A B, A B, A D, E D, A D, A
Note: *See Figure 3-13 on page 3-30 for more information.
A d v an c ed v0 . 5
3-31
ProASIC3 Flash Family FPGAs
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Pad Out
DOUT Y D CC Q EE DFN1E1C1 E BB CLR LL HH AA JJ DD KK Data Input I/O Register with Active high enable Active high clear Positive edge triggered Data Core Array Data_out FF
TRIBUF
INBUF INBUF
D
Q
DFN1E1C1 GG E CLR
EOUT
Enable
CLKBUF
CLK
INBUF
CLR
D
Q
DFN1E1C1 E CLR
INBUF
INBUF
CLKBUF
Data Output Register and Enable Output Register with Active high enable Active high clear Positive edge triggered
D_Enable
Enable
Figure 3-14 * Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
3 -3 2
Advanced v0.5
CLK
ProASIC3 Flash Family FPGAs
Table 3-50 * Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOREMCLR tORECCLR tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEREMCLR tOERECCLR tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIREMCLR tIRECCLR Parameter Definition Clock-to-Q of the Output Data Register Data Setup time for the Output Data Register Data Hold time for the Output Data Register Enable Setup time for the Output Data Register Enable Hold time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Clear Removal time for the Output Data Register Asynchronous Clear Recovery time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup time for the Output Enable Register Data Hold time for the Output Enable Register Enable Setup time for the Output Enable Register Enable Hold time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Clear Removal time for the Output Enable Register Asynchronous Clear Recovery time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup time for the Input Data Register Data Hold time for the Input Data Register Enable Setup time for the Input Data Register Enable Hold time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Clear Removal time for the Input Data Register Asynchronous Clear Recovery time for the Input Data Register Measuring Nodes (From, To)* HH, DOUT FF, HH FF, HH GG, HH GG, HH LL, DOUT LL, HH LL, HH HH, EOUT JJ, HH JJ, HH KK, HH KK, HH II, EOUT II, HH II, HH AA, EE CC, AA CC, AA BB, AA BB, AA DD, EE DD, AA DD, AA
Note: *See Figure 3-14 on page 3-32 for more information.
A d v an c ed v0 . 5
3-33
ProASIC3 Flash Family FPGAs
Input Register
tICKMPWH tICKMPWL 50% 50% tISUD Data 1 50% 0 tIHD 50% 50% 50% 50% 50% 50%
CLK
Enable
50% tIHE 50%
tIWPRE tISUE
tIRECPRE 50% tIWCLR tIRECCLR 50%
tIREMPRE 50% tIREMCLR 50%
Preset
Clear tIPRE2Q Out_1 50% tICLKQ 50%
50%
tICLR2Q
50%
Figure 3-15 * Input Register Timing Diagram
Timing Characteristics
Table 3-51 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup time for the Input Data Register Data Hold time for the Input Data Register Enable Setup time for the Input Data Register Enable Hold time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal time for the Input Data Register Asynchronous Clear Recovery time for the Input Data Register Asynchronous Preset Removal time for the Input Data Register Asynchronous Preset Recovery time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width High for the Input Data Register Clock Minimum Pulse Width Low for the Input Data Register -2 0.63 0.43 0.00 0.43 0.00 0.57 0.45 0.00 0.10 0.00 0.10 0.25 0.25 0.36 0.41 -1 0.71 0.49 0.00 0.49 0.00 0.65 0.51 0.00 0.10 0.00 0.10 0.28 0.28 0.41 0.46 Std. 0.84 0.57 0.00 0.57 0.00 0.76 0.60 0.00 0.10 0.00 0.10 0.33 0.33 0.48 0.54 -F 1.01 0.69 0.00 0.69 0.00 1.01 0.72 0.00 0.10 0.00 0.10 0.40 0.40 0.58 0.65 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3 -3 4
Advanced v0.5
ProASIC3 Flash Family FPGAs
Output Register
tOCKMPWH tOCKMPWL 50% 50% tOSUD tOHD Data_out 1 50% 0 50% 50% 50% 50% 50% 50%
CLK
Enable
50% tOHE 50%
tOWPRE
tORECPRE 50%
t OREMPRE 50%
Preset
tOSUE
tOWCLR Clear tOPRE2Q DOUT 50% tOCLKQ 50% t OCLR2Q 50% 50%
tORECCLR
tOREMCLR 50%
50%
Figure 3-16 * Output Register Timing Diagram
Timing Characteristics
Table 3-52 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup time for the Output Data Register Data Hold time for the Output Data Register Enable Setup time for the Output Data Register Enable Hold time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal time for the Output Data Register Asynchronous Clear Recovery time for the Output Data Register Asynchronous Preset Removal time for the Output Data Register Asynchronous Preset Recovery time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width High for the Output Data Register Clock Minimum Pulse Width Low for the Output Data Register -2 0.63 0.43 0.00 0.43 0.00 0.57 0.45 0.00 0.24 0.00 0.24 0.26 0.26 0.38 0.43 -1 0.71 0.49 0.00 0.49 0.00 0.65 0.51 0.00 0.27 0.00 0.27 0.29 0.29 0.43 0.49 Std. 0.84 0.57 0.00 0.57 0.00 0.76 0.60 0.00 0.32 0.00 0.32 0.34 0.34 0.51 0.57 -F 1.01 0.69 0.00 0.69 0.00 1.01 0.72 0.00 0.38 0.00 0.38 0.41 0.41 0.61 0.69 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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ProASIC3 Flash Family FPGAs
Output Enable Register
tOECKMPWH tOECKMPWL
CLK
50%
50% tOESUD tOEHD
50%
50%
50%
50%
50%
D_Enable
1
50%
0 50%
Enable
50%
tOEWPRE 50%
tOERECPRE 50%
tOEREMPRE 50%
Preset
t tOESUE OEHE
tOEWCLR Clear tOEPRE2Q EOUT 50% tOECLKQ 50% 50%
tOERECCLR 50%
tOEREMCLR 50%
tOECLR2Q 50%
Figure 3-17 * Output Enable Register Timing Diagram
Timing Characteristics
Table 3-53 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWH tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup time for the Output Enable Register Data Hold time for the Output Enable Register Enable Setup time for the Output Enable Register Enable Hold time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal time for the Output Enable Register Asynchronous Clear Recovery time for the Output Enable Register Asynchronous Preset Removal time for the Output Enable Register Asynchronous Preset Recovery time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width High for the Output Enable Register Clock Minimum Pulse Width Low for the Output Enable Register -2 0.63 0.43 0.00 0.43 0.00 0.63 0.45 0.00 0.22 0.00 0.22 0.26 0.26 0.38 0.43 -1 0.71 0.49 0.00 0.49 0.00 0.71 0.51 0.00 0.25 0.00 0.25 0.29 0.29 0.43 0.49 Std. 0.84 0.57 0.00 0.57 0.00 0.84 0.60 0.00 0.30 0.00 0.30 0.34 0.34 0.51 0.57 -F 1.01 0.69 0.00 0.69 0.00 1.01 0.72 0.00 0.36 0.00 0.36 0.41 0.41 0.61 0.69 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3 -3 6
Advanced v0.5
ProASIC3 Flash Family FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
INBUF Data
A FF1
D
Out_QF (To core)
CLK CLKBUF
B FF2
E
Out_QR (To Core)
CLR INBUF
C
DDR_IN
Figure 3-18 * Input DDR Timing Model Table 3-54 * Parameter Definitions Parameter Name tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR Parameter Definition Clock-to-Out Out_QR Clock-to-Out Out_QF Data Setup time of DDR input Data Hold time of DDR input Clear-to-Out Out_QR Clear-to-Out Out_QF Clear Removal Clear Recovery Measuring Nodes (From, To) B, D B, E A, B A, B C, D C, E C, B C, B
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ProASIC3 Flash Family FPGAs
CLK tDDRISUD Data 1 2 3 4 5 6 7 tDDRIHD 8 tDDRIRECCLR CLR t DDRIREMCLR t DDRICLKQ1 t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR 3 2 4 tDDRICLKQ2 5 7 6 9
Table 3-55 * Input DDR Timing Diagram
Timing Characteristics
Table 3-56 * Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR Data Hold for Input DDR Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal time for Input DDR Asynchronous Clear Recovery time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width High for Input DDR Clock Minimum Pulse Width Low for Input DDR Maximum Frequency for Input DDR -2 0.63 0.63 0.53 0.00 0.57 0.57 0.00 0.22 -1 0.71 0.71 0.61 0.00 0.65 0.65 0.00 0.25 Std. 0.84 0.84 0.71 0.00 0.76 0.76 0.00 0.30 -F 1.01 1.01 0.86 0.00 0.91 0.91 0.00 0.36 Units ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3 -3 8
Advanced v0.5
ProASIC3 Flash Family FPGAs
Output DDR Module
Data_F (From Core)
A FF1
CLK CLKBUF
B C D FF2
Out 0 E OUTBUF
Data_R (From Core)
1
CLR INBUF
B C
DDR_OUT
Figure 3-19 * Output DDR Timing Model Table 3-57 * Parameter Definitions Parameter Name tDDROCLKQ tDDROCLR2Q tDDROREMCLR tD DR O REC C L R tD DR O SU D 1 tDDROSUD2 tDDROHD1 tDDROHD2 Clock-to-Out Asynchronous Clear-to-Out Clear Removal Clear Recovery Data Setup Data_F Data Setup Data_R Data Hold Data_F Data Hold Data_R Parameter Definition Measuring Nodes (From, To) B, E C, E C, B C, B A, B D, B A, B D, B
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ProASIC3 Flash Family FPGAs
CLK t Data_F 1 2 tDDROSUD1 Data_R 6 7 t
DDROHD1 DDROSUD2
t
DDROHD2
3
4
5
8
9
10 t DDRORECCLR
11
CLR
tDDROREMCLR tDDROCLR2Q tDDROCLKQ 7 2 8 3 9 4 10
Out
Figure 3-20 * Output DDR Timing Diagram
Timing Characteristics
Table 3-58 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tDDROCLKQ tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal time for Output DDR Asynchronous Clear Recovery time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width High for the Output DDR Clock Minimum Pulse Width Low for the Output DDR Maximum Frequency for the Output DDR -2 0.63 0.43 0.43 0.00 0.00 0.57 0.00 0.22 -1 0.71 0.49 0.49 0.00 0.00 0.65 0.00 0.25 Std. 0.84 0.57 0.57 0.00 0.00 0.76 0.00 0.30 -F 1.01 0.69 0.69 0.00 0.00 0.91 0.00 0.36 Units ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3 -4 0
Advanced v0.5
ProASIC3 Flash Family FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the ProASIC3/E Macro Library Guide.
A
INV
Y
A OR2 B A AND2 B Y Y
A NOR2 B Y
A NAND2 B A B C Y
A B XOR2 Y
XOR3
Y
A A B C B C
MAJ3 Y
A 0 MUX2 B 1 Y
NAND3
S
Figure 3-21 * Sample of Combinatorial Cells
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3-41
ProASIC3 Flash Family FPGAs
t PD
A NAND2 OR Any Combinatorial Logic Y
B
t PD = MAX(t PD(RR), tPD(RF) ), t PD(FF) , tPD(FR) ) where edges are applicable for the particular combinatorial cell VCCA
50% A, B, C
50% GND VCCA 50%
50% OUT GND VCCA OUT 50% t PD (RF)
Figure 3-22 * Timing Model and Waveforms
t PD (RR)
t PD (FF) t PD (FR) GND
50%
3 -4 2
Advanced v0.5
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-59 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=A*B Y = !(A * B) Y=A+B Y = !(A + B) Y=AB Y = MAJ (A , B, C) Y=ABC Y = A !S + B S Y=A*B*C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD -2 0.40 0.47 0.47 0.49 0.49 0.74 0.70 0.87 0.51 0.56 -1 0.46 0.54 0.54 0.55 0.55 0.84 0.79 1.00 0.58 0.64 Std. 0.54 0.63 0.63 0.65 0.65 0.99 0.93 1.17 0.68 0.75 -F 0.65 0.76 0.76 0.78 0.78 1.19 1.12 1.41 0.81 0.90 Units ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells including flip-flops and latches. Each have a data input and optional Enable, Clear, or Preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the ProASIC3/E Macro Library Guide.
Data
D DFN1
Q
Out
Data D En CLK Q DFN1E1
Out
CLK
PRE
Data
D
Q DFN1C1
Out
Data En CLK
D
Q
Out
DFI1E1P1
CLK CLR
Figure 3-23 * Sample of Sequential Cells
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ProASIC3 Flash Family FPGAs
tCKMPWH tCKMPWL 50% 50% tHD tSUD Data 50% 0 50% 50% 50% 50% 50% 50%
CLK
EN 50% tHE PRE t SUE
tWPRE 50%
tRECPRE 50% tRECCLR 50%
tREMPRE 50%
tWCLR CLR tPRE2Q Out tCLKQ
Figure 3-24 * Timing Model and Waveforms
tREMCLR 50%
50%
50%
50%
tCLR2Q 50%
Timing Characteristics
Table 3-60 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Description Clock-to-Q of the Core Register Data Setup time for the Core Register Data Hold time for the Core Register Enable Setup time for the Core Register Enable Hold time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal time for the Core Register Asynchronous Clear Recovery time for the Core Register Asynchronous Preset Removal time for the Core Register Asynchronous Preset Recovery time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width High for the Core Register Clock Minimum Pulse Width Low for the Core Register -2 0.55 0.43 0.00 0.45 0.00 0.40 0.40 0.00 0.22 0.00 0.22 0.26 0.26 0.38 0.43 -1 0.63 0.49 0.00 0.52 0.00 0.45 0.45 0.00 0.25 0.00 0.25 0.29 0.29 0.43 0.49 Std. 0.74 0.57 0.00 0.61 0.00 0.53 0.53 0.00 0.30 0.00 0.30 0.34 0.34 0.51 0.57 -F 0.89 0.69 0.00 0.73 0.00 0.64 0.64 0.00 0.36 0.00 0.36 0.41 0.41 0.61 0.69 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
3 -4 4
Advanced v0.5
ProASIC3 Flash Family FPGAs
Global Resource Characteristics
A3P250 Clock Tree Topology
Clock delays are device-specific. Figure 3-25 is an example of a global tree used for clock routing. The global tree presented in Figure 3-25 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flipflops in the device.
Central Global R
CCC
VersaTil Rows
Global S
Figure 3-25 * Example of Global Tree Use in an A3P250 Device for Clock Routing
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ProASIC3 Flash Family FPGAs
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard dependent and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-15. Table 3-61 to Table 3-66 on page 3-48 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Table 3-61 * A3P060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-62 * A3P125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.14 0.34 0.40 0.47 Min.
1
-1
2
Std.
2
-F
2
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
1
Max. 1.18 1.19
Min.
1
Max. 1.34 1.36
Min.
1
Max. 1.58 1.60
Min.
1
Max.2 Units 1.91 1.91 ns ns ns ns
1.05 1.07
1.02 1.02
1.20 1.21
1.44 1.45
0.14
0.34
0.40
0.47
ns MHz
-1 Min.1 1.08 1.07 Max.2 1.40 1.41
Std. Min.1 1.26 1.26 Max.2 1.64 1.66
-F Min.1 1.52 1.52 Max.2 Units 1.99 1.98 ns ns ns ns ns MHz
Max.2 1.23 1.24
1.10 1.12
3 -4 6
Advanced v0.5
ProASIC3 Flash Family FPGAs
Table 3-63 * A3P250 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-64 * A3P400 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.13 0.34 0.40 0.47 Min.
1
-1
2
Std.
2
-F
2
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
1
Max. 1.22 1.24
Min.
1
Max. 1.40 1.41
Min.
1
Max. 1.64 1.65
Min.
1
Max.2 Units 1.99 1.98 ns ns ns ns
1.10 1.11
1.07 1.07
1.26 1.26
1.52 1.52
0.14
0.34
0.39
0.47
ns MHz
-1 Min.1 1.13 1.12 Max.2 1.45 1.46
Std. Min.1 1.33 1.32 Max.2 1.70 1.72
-F Min.1 1.59 1.59 Max.2 Units 2.06 2.05 ns ns ns ns ns Mhz
Max.2 1.27 1.28
1.15 1.16
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ProASIC3 Flash Family FPGAs
Table 3-65 * A3P600 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-66 * A3P1000 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.13 0.33 0.39 0.47 Min.
1
-1
2
Std.
2
-F
2
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
1
Max. 1.27 1.28
Min.
1
Max. 1.45 1.46
Min.
1
Max. 1.70 1.72
Min.
1
Max.2 Units 2.06 2.05 ns ns ns ns
1.15 1.16
1.13 1.12
1.33 1.32
1.59 1.59
0.13
0.34
0.40
0.47
ns MHz
-1 Min.1 1.18 1.18 Max.2 1.50 1.51
Std. Min.1 1.39 1.38 Max.2 1.76 1.77
-F Min.1 1.67 1.66 Max.2 Units 2.13 2.12 ns ns ns ns ns MHz
Max.2 1.32 1.32
1.19 1.20
3 -4 8
Advanced v0.5
ProASIC3 Flash Family FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0 RAM512X18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0
DINA0
RW1 RW0
WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0
PIPE
REN RCLK WADDR8 WADDR7
WADDR0 WD17 WD16
WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0
WEN WCLK RESET
Figure 3-26 * RAM Models
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ProASIC3 Flash Family FPGAs
Timing Waveforms
tCYC tCKH CLK tAS ADD tBKS BLK_B tENS WEN_B tCKQ1 DO Dn D0 tDOH1
Figure 3-27 * RAM Read for Flow-Through Output
tCKL
tAH A0 A1 A2 tBKH tENH
D1
D2
tCYC tCKH CLK tAS ADD t BKS BLK_B t ENS WEN_B tCKQ2 DO Dn D0 tDOH2
Figure 3-28 * RAM Read for Pipelined Output
tCKL
tAH A0 A1 A2 tBKH tENH
D1
3 -5 0
Advanced v0.5
ProASIC3 Flash Family FPGAs
tCYC tCKH CLK tAS ADD A0 t BKS t BLK_B tENS WEN_B t DI DI0
DS BKH
t CKL
tAH A1 A2
t ENH
t DI1
DH
DO
Figure 3-29 * RAM Write, Output Retained (WMODE = 0)
Dn
D2
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ProASIC3 Flash Family FPGAs
tCYC tCKH CLK tAS ADD tBKS BLK_B tENS WEN_B tDS DI DO (flow-through) DO (Pipelined) DI0 tDH DI1 DI2 t BKH A0 tAH A1 A2 tCKL
Dn
DI0
DI1
Dn
DI0
DI1
Figure 3-30 * RAM Write, Output as Write Data (WMODE = 1)
3 -5 2
Advanced v0.5
ProASIC3 Flash Family FPGAs
CLK1 tAS ADD1 tDS DI1 tAH A0 tDH D0 t WRO CLK2 tAS ADD2 A0 tCKQ1 Dn D0 tCKQ2 Dn D0 D1 A1 tAH A4 D2 D3 A2 A3
DO2 (flow-through) DO2 (Pipelined)
Figure 3-31 * One Port Write/Other Port Read Same
tCYC t CKH CLK t CKL
RESET_B t RSTBQ DO Dm Dn
Figure 3-32 * RAM Reset
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ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-67 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC Address Setup time Address Hold time REN_B,WEN_B Setup time REN_B, WEN_B Hold time BLK_B Setup time BLK_B Hold time Input data (DI) Setup time Input data (DI) Hold time Clock High to New Data Valid on DO (output retained, WMODE = 0) Clock High to New Data Valid on DO (flow-through, WMODE = 1) Clock HIGH to New Data Valid on DO (pipelined) RESET_B Low to Data Out Low on DO (flow through) RESET_B Low to Data Out Low on DO (pipelined) RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle time Description -2 0.25 0.00 0.14 0.10 0.23 0.00 0.18 0.00 1.79 2.36 0.89 0.92 0.92 0.00 0.00 0.22 2.10 -1 0.28 0.00 0.16 0.11 0.27 0.00 0.21 0.00 2.03 2.68 1.02 1.05 1.05 0.00 0.00 0.25 2.38 Std. 0.33 0.00 0.19 0.13 0.31 0.00 0.25 0.00 2.39 3.15 1.20 1.23 1.23 0.00 0.00 0.29 2.80 -F 0.40 0.00 0.23 0.16 0.37 0.00 0.29 0.00 2.87 3.79 1.44 1.48 1.48 0.00 0.00 0.35 3.36 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. Table 3-68 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC Address Setup time Address Hold time REN_B,WEN_B Setup time REB_B, WEN_B Hold time Input data (DI) Setup time Input data (DI) Hold time Clock High to New Data Valid on DO (output retained, WMODE = 0) Clock High to New Data Valid on DO (pipelined) RESET_B Low to Data Out Low on DO (flow through) RESET_B Low to Data Out Low on DO (pipelined) RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle time Description -2 0.25 0.00 0.18 0.06 0.18 0.00 2.16 0.90 0.92 0.92 0.00 0.00 0.22 2.10 -1 0.28 0.00 0.20 0.07 0.21 0.00 2.46 1.02 1.05 1.05 0.00 0.00 0.25 2.38 Std. 0.33 0.00 0.24 0.08 0.25 0.00 2.89 1.20 1.23 1.23 0.00 0.00 0.29 2.80 -F 0.40 0.00 0.28 0.09 0.29 0.00 3.47 1.44 1.48 1.48 0.00 0.00 0.35 3.36 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
FIFO
FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 RD17 RD16
RD0 FULL AFULL EMPTY AEMPTY
AEVAL0 AFVAL11 AFVAL10
AFVAL0 REN RBLK RCLK WD17 WD16
WD0 WEN WBLK WCLK RPIPE
RESET
Figure 3-33 * FIFO Model
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ProASIC3 Flash Family FPGAs
Timing Waveforms
RCLK/ WCLK tMPWRSTB RESET_B tRSTFG EF tRSTAF AEF tRSTFG FF tRSTAF AFF WA/RA (Address Counter)
Figure 3-34 * FIFO Reset
tRSTCK
MATCH (A0)
tCYC RCLK tRCKEF EF tCKAF AEF WA/RA (Address Counter)
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 3-35 * FIFO Reset, Empty Flag, and Almost-Empty Flag
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Advanced v0.5
ProASIC3 Flash Family FPGAs
tCYC WCLK t WCKFF FF t CKAF AFF
WA/RA NO MATCH (Address Counter)
Figure 3-36 * FIFO FULL and AFULL Flag
NO MATCH
Dist = AFF_TH
MATCH (FULL)
WCLK
WA/RA (Address Counter)
MATCH (EMPTY)
NO MATCH
NO MATCH 2nd rising edge after 1st write t RCKEF
NO MATCH
NO MATCH
Dist = AEF_TH + 1
RCLK
1st rising edge after 1st write
EF t CKAF AEF
Figure 3-37 * EMPTY Flag and AEMPTY Flag Deassertion
RCLK WA/RA (Address Counter)
MATCH (FULL)
NO MATCH
NO MATCH 1st rising edge after 2nd read t WCKF
NO MATCH
NO MATCH
Dist = AFF_TH - 1
1st rising edge after 1st read WCLK
FF t CKAF AFF
Figure 3-38 * FULL and ALFULL Deassertion
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ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-69 * FIFO Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B,WEN_B Setup time REN_B, WEN_B Hold time BLK_B Setup time BLK_B Hold time Input data (DI) Setup time Input data (DI) Hold time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag valid RESET_B Low to Almost-Empty/Full Flag Valid RESET_B Low to Data out Low on DO (flow through) RESET_B Low to Data out Low on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle time -2 0.21 0.02 0.25 0.00 0.18 0.00 2.36 0.89 1.72 1.63 3.72 1.69 3.66 0.92 0.92 0.00 0.00 0.21 2.06 -1 0.24 0.02 0.29 0.00 0.21 0.00 2.68 1.02 1.96 1.86 4.24 1.93 4.17 1.05 1.05 0.00 0.00 0.24 2.33 Std. 0.29 0.02 0.34 0.00 0.25 0.00 3.15 1.20 2.30 2.18 4.99 2.27 4.90 1.23 1.23 0.00 0.00 0.29 2.75 -F 0.35 0.03 0.40 0.00 0.29 0.00 3.79 1.44 2.76 2.62 5.99 2.72 5.89 1.48 1.48 0.00 0.00 0.34 3.29 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Embedded FROM Characteristics
tA ADDR A0 tA A1
DO
D0
D1
Figure 3-39 * Timing Diagram
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Advanced v0.5
ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 3-70 * Embedded FROM Access Time Parameter tA Data Access Time Description -2 10 -1 10 Std. 10 Units ns
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected, refer to the I/O Timing characteristics for more details.
Timing Characteristics
Table 3-71 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, worst-case VCC = 1.425 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (Data Out) Reset to Q (Data Out) TCK maximum frequency ResetB Removal time ResetB Recovery time ResetB minimum pulse 20 20 20 -2 -1 Std. Units ns ns ns ns ns ns MHz ns ns ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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ProASIC3 Flash Family FPGAs
Package Pin Assignments
132-Pin QFN
A48 B44 C40 Pin A1 Mark A1 B1 C1 A36 B33 A37 B34 C31
C30
C10 B11 A12
C21 B23 A25
Optional Corner Pad (4x)
C11 B12 A13
C20 B22 A24
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
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ProASIC3 Flash Family FPGAs
100-Pin VQFP
100 1
100-Pin VQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
4 -2
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ProASIC3 Flash Family FPGAs
100-Pin VQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P060 Function GND GAA2/IO51RSB1 IO52RSB1 GAB2/IO53RSB1 IO95RSB1 GAC2/IO94RSB1 IO93RSB1 IO92RSB1 GND GFB1/IO87RSB1 GFB0/IO86RSB1 VCOMPLF GFA0/IO85RSB1 VCCPLF GFA1/IO84RSB1 GFA2/IO83RSB1 VCC VCCIB1 GEC1/IO77RSB1 GEB1/IO75RSB1 GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 VMV1 GNDQ GEA2/IO71RSB1 GEB2/IO70RSB1 GEC2/IO69RSB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO61RSB1
100-Pin VQFP* Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P060 Function VCC GND VCCIB1 IO60RSB1 IO59RSB1 IO58RSB1 GDC2/IO57RSB1 GDB2/IO56RSB1 GDA2/IO55RSB1 IO54RSB1 TCK TDI TMS NC GND VPUMP NC TDO TRST VJTAG GDA1/IO49RSB0 GDC0/IO46RSB0 GDC1/IO45RSB0 IO44RSB0 GCB2/IO42RSB0 GCA0/IO40RSB0 GCA1/IO39RSB0 GCC0/IO36RSB0 GCC1/IO35RSB0 VCCIB0 GND VCC IO31RSB0 GBC2/IO29RSB0 GBB2/IO27RSB0 IO26RSB0
100-Pin VQFP* Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P060 Function GBA2/IO25RSB0 VMV0 GNDQ GBA1/IO24RSB0 GBA0/IO23RSB0 GBB1/IO22RSB0 GBB0/IO21RSB0 GBC1/IO20RSB0 GBC0/IO19RSB0 IO18RSB0 IO17RSB0 IO15RSB0 IO13RSB0 IO11RSB0 VCCIB0 GND VCC IO10RSB0 IO09RSB0 IO08RSB0 GAC1/IO07RSB0 GAC0/IO06RSB0 GAB1/IO05RSB0 GAB0/IO04RSB0 GAA1/IO03RSB0 GAA0/IO02RSB0 IO01RSB0 IO00RSB0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
100-Pin VQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 A3P125 Function GND GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 IO130RSB1 IO129RSB1 GND GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GFA2/IO120RSB1 VCC VCCIB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ GEA2/IO106RSB1 GEB2/IO105RSB1 GEC2/IO104RSB1 IO102RSB1 IO100RSB1 IO99RSB1 IO97RSB1 IO96RSB1 IO95RSB1 IO94RSB1 IO93RSB1 VCC GND
100-Pin VQFP* Pin Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 A3P125 Function VCCIB1 IO87RSB1 IO84RSB1 IO81RSB1 IO75RSB1 GDC2/IO72RSB1 GDB2/IO71RSB1 GDA2/IO70RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO65RSB0 GDC0/IO62RSB0 GDC1/IO61RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 VCCIB0 GND VCC IO47RSB0 GBC2/IO45RSB0 GBB2/IO43RSB0 IO42RSB0 GBA2/IO41RSB0 VMV0 GNDQ GBA1/IO40RSB0
100-Pin VQFP* Pin Number 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P125 Function GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO32RSB0 IO28RSB0 IO25RSB0 IO22RSB0 IO19RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 IO09RSB0 IO07RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
100-Pin VQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P250 Function GND GAA2/IO118UDB3 IO118VDB3 GAB2/IO117UDB3 IO117VDB3 GAC2/IO116UDB3 IO116VDB3 IO112PSB3 GND GFB1/IO109PDB3 GFB0/IO109NDB3 VCOMPLF GFA0/IO108NPB3 VCCPLF GFA1/IO108PPB3 GFA2/IO107PSB3 VCC VCCIB3 GFC2/IO105PSB3 GEC1/IO100PDB3 GEC0/IO100NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 VMV3 GNDQ GEA2/IO97RSB2 GEB2/IO96RSB2 GEC2/IO95RSB2 IO93RSB2 IO92RSB2 IO91RSB2 IO90RSB2 IO88RSB2 IO86RSB2 IO85RSB2 IO84RSB2
100-Pin VQFP* Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P250 Function VCC GND VCCIB2 IO77RSB2 IO74RSB2 IO71RSB2 GDC2/IO63RSB2 GDB2/IO62RSB2 GDA2/IO61RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP NC TDO TRST VJTAG GDA1/IO60USB1 GDC0/IO58VDB1 GDC1/IO58UDB1 IO52NDB1 GCB2/IO52PDB1 GCA1/IO50PDB1 GCA0/IO50NDB1 GCC0/IO48NDB1 GCC1/IO48PDB1 VCCIB1 GND VCC IO43NDB1 GBC2/IO43PDB1 GBB2/IO42PSB1 IO41NDB1
100-Pin VQFP* Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P250 Function GBA2/IO41PDB1 VMV1 GNDQ GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO29RSB0 IO27RSB0 IO25RSB0 IO23RSB0 IO21RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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4-5
ProASIC3 Flash Family FPGAs
144-Pin TQFP
144 1
144-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
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A d v a n c e d v 0 .5
ProASIC3 Flash Family FPGAs
144-Pin TQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P060 Function GAA2/IO51RSB1 IO52RSB1 GAB2/IO53RSB1 IO95RSB1 GAC2/IO94RSB1 IO93RSB1 IO92RSB1 IO91RSB1 VCC GND VCCIB1 IO90RSB1 GFC1/IO89RSB1 GFC0/IO88RSB1 GFB1/IO87RSB1 GFB0/IO86RSB1 VCOMPLF GFA0/IO85RSB1 VCCPLF GFA1/IO84RSB1 GFA2/IO83RSB1 GFB2/IO82RSB1 GFC2/IO81RSB1 IO80RSB1 IO79RSB1 IO78RSB1 GND VCCIB1 GEC1/IO77RSB1 GEC0/IO76RSB1 GEB1/IO75RSB1 GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 VMV1 GNDQ
144-Pin TQFP* Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P060 Function NC GEA2/IO71RSB1 GEB2/IO70RSB1 GEC2/IO69RSB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 VCC GND VCCIB1 NC IO64RSB1 NC IO63RSB1 NC IO62RSB1 NC IO61RSB1 NC NC IO60RSB1 IO59RSB1 IO58RSB1 GDC2/IO57RSB1 NC GND NC GDB2/IO56RSB1 GDA2/IO55RSB1 IO54RSB1 GNDQ TCK TDI TMS VMV1
144-Pin TQFP* Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3P060 Function VPUMP NC TDO TRST VJTAG GDA0/IO50RSB0 GDB0/IO48RSB0 GDB1/IO47RSB0 VCCIB0 GND IO44RSB0 GCC2/IO43RSB0 GCB2/IO42RSB0 GCA2/IO41RSB0 GCA0/IO40RSB0 GCA1/IO39RSB0 GCB0/IO38RSB0 GCB1/IO37RSB0 GCC0/IO36RSB0 GCC1/IO35RSB0 IO34RSB0 IO33RSB0 NC NC NC VCCIB0 GND VCC IO30RSB0 GBC2/IO29RSB0 IO28RSB0 GBB2/IO27RSB0 IO26RSB0 GBA2/IO25RSB0 VMV0 GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
144-Pin TQFP* Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P060 Function NC NC GBA1/IO24RSB0 GBA0/IO23RSB0 GBB1/IO22RSB0 GBB0/IO21RSB0 GBC1/IO20RSB0 GBC0/IO19RSB0 VCCIB0 GND VCC IO18RSB0 IO17RSB0 IO16RSB0 IO15RSB0 IO14RSB0 IO13RSB0 IO12RSB0 IO11RSB0 NC IO10RSB0 IO09RSB0 IO08RSB0 GAC1/IO07RSB0 GAC0/IO06RSB0 NC GND NC GAB1/IO05RSB0 GAB0/IO04RSB0 GAA1/IO03RSB0 GAA0/IO02RSB0 IO01RSB0 IO00RSB0 GNDQ VMV0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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A d v a n c e d v 0 .5
ProASIC3 Flash Family FPGAs
144_Pin TQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P125 Function GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 IO130RSB1 IO129RSB1 IO128RSB1 VCC GND VCCIB1 IO127RSB1 GFC1/IO126RSB1 GFC0/IO125RSB1 GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GFA2/IO120RSB1 GFB2/IO119RSB1 GFC2/IO118RSB1 IO117RSB1 IO116RSB1 IO115RSB1 GND VCCIB1 GEC1/IO112RSB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ
144_Pin TQFP* Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P125 Function NC GEA2/IO106RSB1 GEB2/IO105RSB1 GEC2/IO104RSB1 IO103RSB1 IO102RSB1 IO101RSB1 IO100RSB1 VCC GND VCCIB1 IO99RSB1 IO97RSB1 IO95RSB1 IO93RSB1 IO92RSB1 IO90RSB1 IO88RSB1 IO86RSB1 IO84RSB1 IO83RSB1 IO82RSB1 IO81RSB1 IO80RSB1 IO79RSB1 VCC GND VCCIB1 GDC2/IO72RSB1 GDB2/IO71RSB1 GDA2/IO70RSB1 GNDQ TCK TDI TMS VMV1
144_Pin TQFP* Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3P125 Function VPUMP NC TDO TRST VJTAG GDA0/IO66RSB0 GDB0/IO64RSB0 GDB1/IO63RSB0 VCCIB0 GND IO60RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GCA2/IO57RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCB0/IO54RSB0 GCB1/IO53RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 IO50RSB0 IO49RSB0 NC NC NC VCCIB0 GND VCC IO47RSB0 GBC2/IO45RSB0 IO44RSB0 GBB2/IO43RSB0 IO42RSB0 GBA2/IO41RSB0 VMV0 GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
144_Pin TQFP* Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P125 Function GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO34RSB0 IO33RSB0 VCCIB0 GND VCC IO29RSB0 IO28RSB0 IO27RSB0 IO25RSB0 IO23RSB0 IO21RSB0 IO19RSB0 IO17RSB0 IO16RSB0 IO14RSB0 IO12RSB0 IO10RSB0 IO08RSB0 IO06RSB0 VCCIB0 GND VCC GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -1 0
Advanced v0.5
ProASIC3 Flash Family FPGAs
208-Pin PQFP
1
208
208-Pin PQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
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ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 A3P125 Function GND GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 NC NC IO130RSB1 IO129RSB1 NC IO128RSB1 NC NC NC VCC GND VCCIB1 IO127RSB1 NC GFC1/IO126RSB1 GFC0/IO125RSB1 GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GND GFA2/IO120RSB1 NC GFB2/IO119RSB1 NC GFC2/IO118RSB1 IO117RSB1 NC IO116RSB1 IO115RSB1
208-Pin PQFP* Pin Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 A3P125 Function NC VCCIB1 GND IO114RSB1 IO113RSB1 GEC1/IO112RSB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ GND NC NC GEA2/IO106RSB1 GEB2/IO105RSB1 GEC2/IO104RSB1 IO103RSB1 IO102RSB1 IO101RSB1 IO100RSB1 VCCIB1 IO99RSB1 IO98RSB1 GND IO97RSB1 IO96RSB1 IO95RSB1 IO94RSB1 IO93RSB1 VCC VCCIB1 IO92RSB1 IO91RSB1 IO90RSB1 IO89RSB1
208-Pin PQFP* Pin Number 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 A3P125 Function IO88RSB1 IO87RSB1 IO86RSB1 IO85RSB1 GND IO84RSB1 IO83RSB1 IO82RSB1 IO81RSB1 IO80RSB1 IO79RSB1 VCC VCCIB1 IO78RSB1 IO77RSB1 IO76RSB1 IO75RSB1 IO74RSB1 IO73RSB1 GDC2/IO72RSB1 GND GDB2/IO71RSB1 GDA2/IO70RSB1 GNDQ TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA0/IO66RSB0 GDA1/IO65RSB0 GDB0/IO64RSB0 GDB1/IO63RSB0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -1 2
Advanced v0.5
ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 A3P125 Function GDC0/IO62RSB0 GDC1/IO61RSB0 NC NC NC NC NC GND VCCIB0 NC NC VCC IO60RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GND GCA2/IO57RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCB0/IO54RSB0 GCB1/IO53RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 IO50RSB0 IO49RSB0 VCCIB0 GND VCC IO48RSB0 IO47RSB0 IO46RSB0 NC NC NC GBC2/IO45RSB0 IO44RSB0 GBB2/IO43RSB0 IO42RSB0
208-Pin PQFP* Pin Number 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 A3P125 Function GBA2/IO41RSB0 VMV0 GNDQ GND NC GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GND GBC1/IO36RSB0 GBC0/IO35RSB0 IO34RSB0 IO33RSB0 IO32RSB0 IO31RSB0 IO30RSB0 VCCIB0 VCC IO29RSB0 IO28RSB0 IO27RSB0 IO26RSB0 IO25RSB0 IO24RSB0 GND IO23RSB0 IO22RSB0 IO21RSB0 IO20RSB0 IO19RSB0 IO18RSB0 IO17RSB0 VCCIB0 VCC IO16RSB0 IO15RSB0 IO14RSB0
208-Pin PQFP* Pin Number 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A3P125 Function IO13RSB0 IO12RSB0 IO11RSB0 IO10RSB0 GND IO09RSB0 IO08RSB0 IO07RSB0 IO06RSB0 VCCIB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P250 Function GND GAA2/IO118UDB3 IO118VDB3 GAB2/IO117UDB3 IO117VDB3 GAC2/IO116UDB3 IO116VDB3 IO115UDB3 IO115VDB3 IO114UDB3 IO114VDB3 IO113PDB3 IO113NDB3 IO112PDB3 IO112NDB3 VCC GND VCCIB3 IO111PDB3 IO111NDB3 GFC1/IO110PDB3 GFC0/IO110NDB3 GFB1/IO109PDB3 GFB0/IO109NDB3 VCOMPLF GFA0/IO108NPB3 VCCPLF GFA1/IO108PPB3 GND GFA2/IO107PDB3 IO107NDB3 GFB2/IO106PDB3 IO106NDB3 GFC2/IO105PDB3 IO105NDB3 NC
208-Pin PQFP* Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P250 Function IO104PDB3 IO104NDB3 IO103PSB3 VCCIB3 GND IO101PDB3 IO101NDB3 GEC1/IO100PDB3 GEC0/IO100NDB3 GEB1/IO99PDB3 GEB0/IO99NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 VMV3 GNDQ GND NC NC GEA2/IO97RSB2 GEB2/IO96RSB2 GEC2/IO95RSB2 IO94RSB2 IO93RSB2 IO92RSB2 IO91RSB2 VCCIB2 IO90RSB2 IO89RSB2 GND IO88RSB2 IO87RSB2 IO86RSB2 IO85RSB2 IO84RSB2 VCC VCCIB2
208-Pin PQFP* Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3P250 Function IO83RSB2 IO82RSB2 IO81RSB2 IO80RSB2 IO79RSB2 IO78RSB2 IO77RSB2 IO76RSB2 GND IO75RSB2 IO74RSB2 IO73RSB2 IO72RSB2 IO71RSB2 IO70RSB2 VCC VCCIB2 IO69RSB2 IO68RSB2 IO67RSB2 IO66RSB2 IO65RSB2 IO64RSB2 GDC2/IO63RSB2 GND GDB2/IO62RSB2 GDA2/IO61RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP NC TDO
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P250 Function TRST VJTAG GDA0/IO60VDB1 GDA1/IO60UDB1 GDB0/IO59VDB1 GDB1/IO59UDB1 GDC0/IO58VDB1 GDC1/IO58UDB1 IO57VDB1 IO57UDB1 IO56NDB1 IO56PDB1 IO55RSB1 GND VCCIB1 NC NC VCC IO53NDB1 GCC2/IO53PDB1 GCB2/IO52PSB1 GND GCA2/IO51PSB1 GCA1/IO50PDB1 GCA0/IO50NDB1 GCB0/IO49NDB1 GCB1/IO49PDB1 GCC0/IO48NDB1 GCC1/IO48PDB1 IO47NDB1 IO47PDB1 VCCIB1 GND VCC IO46RSB1 IO45NDB1
208-Pin PQFP* Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 A3P250 Function IO45PDB1 IO44NDB1 IO44PDB1 IO43NDB1 GBC2/IO43PDB1 IO42NDB1 GBB2/IO42PDB1 IO41NDB1 GBA2/IO41PDB1 VMV1 GNDQ GND NC GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GND GBC1/IO36RSB0 GBC0/IO35RSB0 IO34RSB0 IO33RSB0 IO32RSB0 IO31RSB0 IO30RSB0 VCCIB0 VCC IO29RSB0 IO28RSB0 IO27RSB0 IO26RSB0 IO25RSB0 IO24RSB0 GND IO23RSB0 IO22RSB0
208-Pin PQFP* Pin Number 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A3P250 Function IO21RSB0 IO20RSB0 IO19RSB0 IO18RSB0 IO17RSB0 VCCIB0 VCC IO16RSB0 IO15RSB0 IO14RSB0 IO13RSB0 IO12RSB0 IO11RSB0 IO10RSB0 GND IO09RSB0 IO08RSB0 IO07RSB0 IO06RSB0 VCCIB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 A3P400 Function GND GAA2/IO155PDB3 IO155NDB3 GAB2/IO154PDB3 IO154NDB3 GAC2/IO153PDB3 IO153NDB3 IO152PDB3 IO152NDB3 IO151PDB3 IO151NDB3 IO150PDB3 IO150NDB3 IO149PDB3 IO149NDB3 VCC GND VCCIB3 IO148PDB3 IO148NDB3 GFC1/IO147PDB3 GFC0/IO147NDB3 GFB1/IO146PDB3 GFB0/IO146NDB3 VCOMPLF GFA0/IO145NPB3 VCCPLF GFA1/IO145PPB3 GND GFA2/IO144PDB3 IO144NDB3 GFB2/IO143PDB3 IO143NDB3 GFC2/IO142PDB3 IO142NDB3 NC IO141PDB3 IO141NDB3
208-Pin PQFP* Pin Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 A3P400 Function IO140PSB3 VCCIB3 GND IO138PDB3 IO138NDB3 GEC1/IO137PDB3 GEC0/IO137NDB3 GEB1/IO136PDB3 GEB0/IO136NDB3 GEA1/IO135PDB3 GEA0/IO135NDB3 VMV3 GNDQ GND NC NC GEA2/IO134RSB2 GEB2/IO133RSB2 GEC2/IO132RSB2 IO131RSB2 IO130RSB2 IO129RSB2 IO128RSB2 VCCIB2 IO126RSB2 IO124RSB2 GND IO122RSB2 IO120RSB2 IO118RSB2 IO116RSB2 IO114RSB2 VCC VCCIB2 IO112RSB2 IO111RSB2 IO110RSB2 IO109RSB2
208-Pin PQFP* Pin Number 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 A3P400 Function IO108RSB2 IO107RSB2 IO106RSB2 IO103RSB2 GND IO102RSB2 IO101RSB2 IO100RSB2 IO99RSB2 IO98RSB2 IO97RSB2 VCC VCCIB2 IO94RSB2 IO92RSB2 IO90RSB2 IO88RSB2 IO86RSB2 IO84RSB2 GDC2/IO82RSB2 GND GDB2/IO81RSB2 GDA2/IO80RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP NC TDO TRST VJTAG GDA0/IO79NDB1 GDA1/IO79PDB1 GDB0/IO78NDB1 GDB1/IO78PDB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -1 6
Advanced v0.5
ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 A3P400 Function GDC0/IO77NDB1 GDC1/IO77PDB1 IO76NDB1 IO76PDB1 IO75NDB1 IO75PDB1 IO74RSB1 GND VCCIB1 NC NC VCC IO73PSB1 GCC2/IO72PSB1 GCB2/IO71PSB1 GND GCA2/IO70PSB1 GCA1/IO69PDB1 GCA0/IO69NDB1 GCB0/IO68NDB1 GCB1/IO68PDB1 GCC0/IO67NDB1 GCC1/IO67PDB1 IO66NDB1 IO66PDB1 VCCIB1 GND VCC IO65RSB1 IO64NDB1 IO64PDB1 IO63NDB1 IO63PDB1 IO62NDB1 GBC2/IO62PDB1 IO61NDB1 GBB2/IO61PDB1 IO60NDB1
208-Pin PQFP* Pin Number 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 A3P400 Function GBA2/IO60PDB1 VMV1 GNDQ GND NC GBA1/IO59RSB0 GBA0/IO58RSB0 GBB1/IO57RSB0 GBB0/IO56RSB0 GND GBC1/IO55RSB0 GBC0/IO54RSB0 IO52RSB0 IO50RSB0 IO48RSB0 IO46RSB0 IO44RSB0 VCCIB0 VCC IO37RSB0 IO36RSB0 IO35RSB0 IO34RSB0 IO33RSB0 IO32RSB0 GND IO31RSB0 IO30RSB0 IO29RSB0 IO28RSB0 IO27RSB0 IO25RSB0 IO23RSB0 VCCIB0 VCC IO19RSB0 IO17RSB0 IO15RSB0
208-Pin PQFP* Pin Number 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A3P400 Function IO13RSB0 IO12RSB0 IO11RSB0 IO10RSB0 GND IO09RSB0 IO08RSB0 IO07RSB0 IO06RSB0 VCCIB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 A3P600 Function GND GAA2/IO170PDB3 IO170NDB3 GAB2/IO169PDB3 IO169NDB3 GAC2/IO168PDB3 IO168NDB3 IO167PDB3 IO167NDB3 IO166PDB3 IO166NDB3 IO165PDB3 IO165NDB3 IO164PDB3 IO164NDB3 VCC GND VCCIB3 IO163PDB3 IO163NDB3 GFC1/IO161PDB3 GFC0/IO161NDB3 GFB1/IO160PDB3 GFB0/IO160NDB3 VCOMPLF GFA0/IO159NPB3 VCCPLF GFA1/IO159PPB3 GND GFA2/IO158PDB3 IO158NDB3 GFB2/IO157PDB3 IO157NDB3 GFC2/IO156PDB3 IO156NDB3 VCC IO147PDB3 IO147NDB3
208-Pin PQFP* Pin Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 A3P600 Function IO146PSB3 VCCIB3 GND IO145PDB3 IO145NDB3 GEC1/IO144PDB3 GEC0/IO144NDB3 GEB1/IO143PDB3 GEB0/IO143NDB3 GEA1/IO142PDB3 GEA0/IO142NDB3 VMV3 GNDQ GND NC GEA2/IO141RSB2 GEB2/IO140RSB2 GEC2/IO139RSB2 IO138RSB2 IO137RSB2 IO136RSB2 IO135RSB2 IO134RSB2 VCCIB2 IO133RSB2 IO131RSB2 GND IO129RSB2 IO127RSB2 IO125RSB2 IO123RSB2 IO121RSB2 VCC VCCIB2 IO118RSB2 IO117RSB2 IO116RSB2 IO115RSB2
208-Pin PQFP* Pin Number 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 A3P600 Function IO114RSB2 IO113RSB2 IO112RSB2 IO110RSB2 GND IO109RSB2 IO108RSB2 IO107RSB2 IO106RSB2 IO105RSB2 IO104RSB2 VCC VCCIB2 IO102RSB2 IO100RSB2 IO98RSB2 IO96RSB2 IO94RSB2 IO90RSB2 GDC2/IO89RSB2 GND GDB2/IO88RSB2 GDA2/IO87RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP GNDQ TDO TRST VJTAG GDA0/IO86NDB1 GDA1/IO86PDB1 GDB0/IO85NDB1 GDB1/IO85PDB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 A3P600 Function GDC0/IO84NDB1 GDC1/IO84PDB1 IO82NDB1 IO82PDB1 IO80NDB1 IO80PDB1 IO79PSB1 GND VCCIB1 IO75NDB1 IO75PDB1 NC IO73NDB1 GCC2/IO73PDB1 GCB2/IO72PSB1 GND GCA2/IO71PSB1 GCA1/IO70PDB1 GCA0/IO70NDB1 GCB0/IO69NDB1 GCB1/IO69PDB1 GCC0/IO68NDB1 GCC1/IO68PDB1 IO66NDB1 IO66PDB1 VCCIB1 GND VCC IO65PSB1 IO64NDB1 IO64PDB1 IO63NDB1 IO63PDB1 IO62NDB1 GBC2/IO62PDB1 IO61NDB1 GBB2/IO61PDB1 IO60NDB1
208-Pin PQFP* Pin Number 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 A3P600 Function GBA2/IO60PDB1 VMV1 GNDQ GND NC GBA1/IO59RSB0 GBA0/IO58RSB0 GBB1/IO57RSB0 GBB0/IO56RSB0 GND GBC1/IO55RSB0 GBC0/IO54RSB0 IO52RSB0 IO50RSB0 IO48RSB0 IO46RSB0 IO44RSB0 VCCIB0 VCC IO36RSB0 IO35RSB0 IO34RSB0 IO33RSB0 IO32RSB0 IO31RSB0 GND IO29RSB0 IO28RSB0 IO27RSB0 IO26RSB0 IO25RSB0 IO24RSB0 IO23RSB0 VCCIB0 VCC IO20RSB0 IO19RSB0 IO18RSB0
208-Pin PQFP* Pin Number 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A3P600 Function IO17RSB0 IO16RSB0 IO14RSB0 IO12RSB0 GND IO10RSB0 IO09RSB0 IO08RSB0 IO07RSB0 VCCIB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3P1000 Function GND GAA2/IO225PDB3 IO225NDB3 GAB2/IO224PDB3 IO224NDB3 GAC2/IO223PDB3 IO223NDB3 IO222PDB3 IO222NDB3 IO220PDB3 IO220NDB3 IO218PDB3 IO218NDB3 IO216PDB3 IO216NDB3 VCC GND VCCIB3 IO212PDB3 IO212NDB3 GFC1/IO209PDB3 GFC0/IO209NDB3 GFB1/IO208PDB3 GFB0/IO208NDB3 VCOMPLF GFA0/IO207NPB3 VCCPLF GFA1/IO207PPB3 GND GFA2/IO206PDB3 IO206NDB3 GFB2/IO205PDB3 IO205NDB3 GFC2/IO204PDB3 IO204NDB3 Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
208-Pin PQFP* A3P1000 Function VCC IO199PDB3 IO199NDB3 IO197PSB3 VCCIB3 GND IO191PDB3 IO191NDB3 GEC1/IO190PDB3 GEC0/IO190NDB3 GEB1/IO189PDB3 GEB0/IO189NDB3 GEA1/IO188PDB3 GEA0/IO188NDB3 VMV3 GNDQ GND VMV2 GEA2/IO187RSB2 GEB2/IO186RSB2 GEC2/IO185RSB2 IO184RSB2 IO183RSB2 IO182RSB2 IO181RSB2 IO180RSB2 VCCIB2 IO178RSB2 IO176RSB2 GND IO174RSB2 IO172RSB2 IO170RSB2 IO168RSB2 IO166RSB2 Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
208-Pin PQFP* A3P1000 Function VCC VCCIB2 IO162RSB2 IO160RSB2 IO158RSB2 IO156RSB2 IO154RSB2 IO152RSB2 IO150RSB2 IO148RSB2 GND IO143RSB2 IO141RSB2 IO139RSB2 IO137RSB2 IO135RSB2 IO133RSB2 VCC VCCIB2 IO128RSB2 IO126RSB2 IO124RSB2 IO122RSB2 IO120RSB2 IO118RSB2 GDC2/IO116RSB2 GND GDB2/IO115RSB2 GDA2/IO114RSB2 GNDQ TCK TDI TMS VMV2 GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -2 0
Advanced v0.5
ProASIC3 Flash Family FPGAs
208-Pin PQFP* Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 A3P1000 Function VPUMP GNDQ TDO TRST VJTAG GDA0/IO113NDB1 GDA1/IO113PDB1 GDB0/IO112NDB1 GDB1/IO112PDB1 GDC0/IO111NDB1 GDC1/IO111PDB1 IO109NDB1 IO109PDB1 IO106NDB1 IO106PDB1 IO104PSB1 GND VCCIB1 IO99NDB1 IO99PDB1 NC IO96NDB1 GCC2/IO96PDB1 GCB2/IO95PSB1 GND GCA2/IO94PSB1 GCA1/IO93PDB1 GCA0/IO93NDB1 GCB0/IO92NDB1 GCB1/IO92PDB1 GCC0/IO91NDB1 GCC1/IO91PDB1 IO88NDB1 IO88PDB1 VCCIB1 Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
208-Pin PQFP* A3P1000 Function GND VCC IO86PSB1 IO84NDB1 IO84PDB1 IO82NDB1 IO82PDB1 IO80NDB1 GBC2/IO80PDB1 IO79NDB1 GBB2/IO79PDB1 IO78NDB1 GBA2/IO78PDB1 VMV1 GNDQ GND VMV0 GBA1/IO77RSB0 GBA0/IO76RSB0 GBB1/IO75RSB0 GBB0/IO74RSB0 GND GBC1/IO73RSB0 GBC0/IO72RSB0 IO70RSB0 IO67RSB0 IO63RSB0 IO60RSB0 IO57RSB0 VCCIB0 VCC IO54RSB0 IO51RSB0 IO48RSB0 IO45RSB0 Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
208-Pin PQFP* A3P1000 Function IO42RSB0 IO40RSB0 GND IO38RSB0 IO35RSB0 IO33RSB0 IO31RSB0 IO29RSB0 IO27RSB0 IO25RSB0 VCCIB0 VCC IO22RSB0 IO20RSB0 IO18RSB0 IO16RSB0 IO15RSB0 IO14RSB0 IO13RSB0 GND IO12RSB0 IO11RSB0 IO10RSB0 IO09RSB0 VCCIB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
144-Pin FBGA
A1 Ball Pad Corner
12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
4 -2 2
Advanced v0.5
ProASIC3 Flash Family FPGAs
144-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P060 Function GNDQ VMV0 GAB0/IO04RSB0 GAB1/IO05RSB0 IO08RSB0 GND IO11RSB0 VCC IO16RSB0 GBA0/IO23RSB0 GBA1/IO24RSB0 GNDQ GAB2/IO53RSB1 GND GAA0/IO02RSB0 GAA1/IO03RSB0 IO00RSB0 IO10RSB0 IO12RSB0 IO14RSB0 GBB0/IO21RSB0 GBB1/IO22RSB0 GND VMV0 IO95RSB1 GFA2/IO83RSB1 GAC2/IO94RSB1 VCC IO01RSB0 IO09RSB0 IO13RSB0 IO15RSB0 IO17RSB0 GBA2/IO25RSB0 IO26RSB0 GBC2/IO29RSB0
144-Pin FBGA* Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P060 Function IO91RSB1 IO92RSB1 IO93RSB1 GAA2/IO51RSB1 GAC0/IO06RSB0 GAC1/IO07RSB0 GBC0/IO19RSB0 GBC1/IO20RSB0 GBB2/IO27RSB0 IO18RSB0 IO28RSB0 GCB1/IO37RSB0 VCC GFC0/IO88RSB1 GFC1/IO89RSB1 VCCIB1 IO52RSB1 VCCIB0 VCCIB0 GCC1/IO35RSB0 VCCIB0 VCC GCA0/IO40RSB0 IO30RSB0 GFB0/IO86RSB1 VCOMPLF GFB1/IO87RSB1 IO90RSB1 GND GND GND GCC0/IO36RSB0 GCB0/IO38RSB0 GND GCA1/IO39RSB0 GCA2/IO41RSB0
144-Pin FBGA* Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P060 Function GFA1/IO84RSB1 GND VCCPLF GFA0/IO85RSB1 GND GND GND GDC1/IO45RSB0 IO32RSB0 GCC2/IO43RSB0 IO31RSB0 GCB2/IO42RSB0 VCC GFB2/IO82RSB1 GFC2/IO81RSB1 GEC1/IO77RSB1 VCC IO34RSB0 IO44RSB0 GDB2/IO56RSB1 GDC0/IO46RSB0 VCCIB0 IO33RSB0 VCC GEB1/IO75RSB1 IO78RSB1 VCCIB1 GEC0/IO76RSB1 IO79RSB1 IO80RSB1 VCC TCK GDA2/IO55RSB1 TDO GDA1/IO49RSB0 GDB1/IO47RSB0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
144-Pin FBGA* Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P060 Function GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 GEA2/IO71RSB1 IO65RSB1 IO64RSB1 GND IO54RSB1 GDC2/IO57RSB1 GND GDA0/IO50RSB0 GDB0/IO48RSB0 GND VMV1 GEB2/IO70RSB1 IO67RSB1 VCCIB1 IO62RSB1 IO59RSB1 IO58RSB1 TMS VJTAG VMV1 TRST GNDQ GEC2/IO69RSB1 IO68RSB1 IO66RSB1 IO63RSB1 IO61RSB1 IO60RSB1 NC TDI VCCIB1 VPUMP GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P250 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO16RSB0 GND IO29RSB0 VCC IO33RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GNDQ GAB2/IO117UDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO14RSB0 IO19RSB0 IO22RSB0 IO30RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GND VMV1 IO117VDB3 GFA2/IO107PPB3 GAC2/IO116UDB3 VCC IO12RSB0 IO17RSB0 IO24RSB0 IO31RSB0 IO34RSB0 GBA2/IO41PDB1 IO41NDB1 GBC2/IO43PPB1
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P250 Function IO112NDB3 IO112PDB3 IO116VDB3 GAA2/IO118UPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO35RSB0 GBC1/IO36RSB0 GBB2/IO42PDB1 IO42NDB1 IO43NPB1 GCB1/IO49PPB1 VCC GFC0/IO110NDB3 GFC1/IO110PDB3 VCCIB3 IO118VPB3 VCCIB0 VCCIB0 GCC1/IO48PDB1 VCCIB1 VCC GCA0/IO50NDB1 IO51NDB1 GFB0/IO109NPB3 VCOMPLF GFB1/IO109PPB3 IO107NPB3 GND GND GND GCC0/IO48NDB1 GCB0/IO49NPB1 GND GCA1/IO50PDB1 GCA2/IO51PDB1
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P250 Function GFA1/IO108PPB3 GND VCCPLF GFA0/IO108NPB3 GND GND GND GDC1/IO58UPB1 IO53NDB1 GCC2/IO53PDB1 IO52NDB1 GCB2/IO52PDB1 VCC GFB2/IO106PDB3 GFC2/IO105PSB3 GEC1/IO100PDB3 VCC IO79RSB2 IO65RSB2 GDB2/IO62RSB2 GDC0/IO58VPB1 VCCIB1 IO54PSB1 VCC GEB1/IO99PDB3 IO106NDB3 VCCIB3 GEC0/IO100NDB3 IO88RSB2 IO81RSB2 VCC TCK GDA2/IO61RSB2 TDO GDA1/IO60UDB1 GDB1/IO59UDB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P250 Function GEB0/IO99NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 GEA2/IO97RSB2 IO90RSB2 IO84RSB2 GND IO66RSB2 GDC2/IO63RSB2 GND GDA0/IO60VDB1 GDB0/IO59VDB1 GND VMV3 GEB2/IO96RSB2 IO91RSB2 VCCIB2 IO82RSB2 IO80RSB2 IO72RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO95RSB2 IO92RSB2 IO89RSB2 IO87RSB2 IO85RSB2 IO78RSB2 IO76RSB2 TDI VCCIB2 VPUMP GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
144-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P1000 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO10RSB0 GND IO44RSB0 VCC IO69RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GNDQ GAB2/IO224PDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO13RSB0 IO26RSB0 IO35RSB0 IO60RSB0 GBB0/IO74RSB0 GBB1/IO75RSB0 GND VMV1 IO224NDB3 GFA2/IO206PPB3 GAC2/IO223PDB3 VCC IO16RSB0 IO29RSB0 IO32RSB0 IO63RSB0 IO66RSB0 GBA2/IO78PDB1 IO78NDB1 GBC2/IO80PPB1
144-Pin FBGA* Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P1000 Function IO213PDB3 IO213NDB3 IO223NDB3 GAA2/IO225PPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO72RSB0 GBC1/IO73RSB0 GBB2/IO79PDB1 IO79NDB1 IO80NPB1 GCB1/IO92PPB1 VCC GFC0/IO209NDB3 GFC1/IO209PDB3 VCCIB3 IO225NPB3 VCCIB0 VCCIB0 GCC1/IO91PDB1 VCCIB1 VCC GCA0/IO93NDB1 IO94NDB1 GFB0/IO208NPB3 VCOMPLF GFB1/IO208PPB3 IO206NPB3 GND GND GND GCC0/IO91NDB1 GCB0/IO92NPB1 GND GCA1/IO93PDB1 GCA2/IO94PDB1
144-Pin FBGA* Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P1000 Function GFA1/IO207PPB3 GND VCCPLF GFA0/IO207NPB3 GND GND GND GDC1/IO111PPB1 IO96NDB1 GCC2/IO96PDB1 IO95NDB1 GCB2/IO95PDB1 VCC GFB2/IO205PDB3 GFC2/IO204PSB3 GEC1/IO190PDB3 VCC IO105PDB1 IO105NDB1 GDB2/IO115RSB2 GDC0/IO111NPB1 VCCIB1 IO101PSB1 VCC GEB1/IO189PDB3 IO205NDB3 VCCIB3 GEC0/IO190NDB3 IO160RSB2 IO157RSB2 VCC TCK GDA2/IO114RSB2 TDO GDA1/IO113PDB1 GDB1/IO112PDB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
144-Pin FBGA* Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P1000 Function GEB0/IO189NDB3 GEA1/IO188PDB3 GEA0/IO188NDB3 GEA2/IO187RSB2 IO169RSB2 IO152RSB2 GND IO117RSB2 GDC2/IO116RSB2 GND GDA0/IO113NDB1 GDB0/IO112NDB1 GND VMV3 GEB2/IO186RSB2 IO172RSB2 VCCIB2 IO153RSB2 IO144RSB2 IO140RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO185RSB2 IO173RSB2 IO168RSB2 IO161RSB2 IO156RSB2 IO145RSB2 IO141RSB2 TDI VCCIB2 VPUMP GNDQ
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
256-Pin FBGA
A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 654 321 A B C D E F G H J K L M N P R T
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
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ProASIC3 Flash Family FPGAs
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 A3P250 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO07RSB0 IO10RSB0 IO11RSB0 IO15RSB0 IO20RSB0 IO25RSB0 IO29RSB0 IO33RSB0 GBB1/IO38RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GND GAB2/IO117UDB3 GAA2/IO118UDB3 NC GAB1/IO03RSB0 IO06RSB0 IO09RSB0 IO12RSB0 IO16RSB0 IO21RSB0 IO26RSB0 IO30RSB0 GBC1/IO36RSB0 GBB0/IO37RSB0 NC GBA2/IO41PDB1 IO41NDB1 IO117VDB3 IO118VDB3 NC
256-Pin FBGA Pin Number C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 A3P250 Function NC GAC0/IO04RSB0 GAC1/IO05RSB0 IO13RSB0 IO17RSB0 IO22RSB0 IO27RSB0 IO31RSB0 GBC0/IO35RSB0 IO34RSB0 NC IO42NPB1 IO44PDB1 IO114VDB3 IO114UDB3 GAC2/IO116UDB3 NC GNDQ IO08RSB0 IO14RSB0 IO18RSB0 IO23RSB0 IO28RSB0 IO32RSB0 GNDQ NC GBB2/IO42PPB1 NC IO44NDB1 IO113PDB3 NC IO116VDB3 IO115UDB3 VMV0 VCCIB0
256-Pin FBGA Pin Number E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 A3P250 Function VCCIB0 IO19RSB0 IO24RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO43PDB1 IO46RSB1 NC IO45PDB1 IO113NDB3 IO112PPB3 NC IO115VDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO43NDB1 NC IO47PPB1 IO45NDB1 IO111NDB3 IO111PDB3 IO112NPB3 GFC1/IO110PPB3 VCCIB3 VCC GND GND GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -3 0
Advanced v0.5
ProASIC3 Flash Family FPGAs
256-Pin FBGA Pin Number G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P250 Function GND VCC VCCIB1 GCC1/IO48PPB1 IO47NPB1 IO54PDB1 IO54NDB1 GFB0/IO109NPB3 GFA0/IO108NDB3 GFB1/IO109PPB3 VCOMPLF GFC0/IO110NPB3 VCC GND GND GND GND VCC GCC0/IO48NPB1 GCB1/IO49PPB1 GCA0/IO50NPB1 NC GCB0/IO49NPB1 GFA2/IO107PPB3 GFA1/IO108PDB3 VCCPLF IO106NDB3 GFB2/IO106PDB3 VCC GND GND GND GND VCC GCB2/IO52PPB1
256-Pin FBGA Pin Number J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 A3P250 Function GCA1/IO50PPB1 GCC2/IO53PPB1 NC GCA2/IO51PDB1 GFC2/IO105PDB3 IO107NPB3 IO104PPB3 NC VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO52NPB1 IO55RSB1 IO53NPB1 IO51NDB1 IO105NDB3 IO104NPB3 NC IO102RSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO59VPB1 IO57VDB1 IO57UDB1
256-Pin FBGA Pin Number L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 A3P250 Function IO56PDB1 IO103PDB3 NC IO101NPB3 GEC0/IO100NPB3 VMV3 VCCIB2 VCCIB2 NC IO74RSB2 VCCIB2 VCCIB2 VMV2 NC GDB1/IO59UPB1 GDC1/IO58UDB1 IO56NDB1 IO103NDB3 IO101PPB3 GEC1/IO100PPB3 NC GNDQ GEA2/IO97RSB2 IO86RSB2 IO82RSB2 IO75RSB2 IO69RSB2 IO64RSB2 GNDQ NC VJTAG GDC0/IO58VDB1 GDA1/IO60UDB1 GEB1/IO99PDB3 GEB0/IO99NDB3
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
256-Pin FBGA Pin Number P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 A3P250 Function NC NC IO92RSB2 IO89RSB2 IO85RSB2 IO81RSB2 IO76RSB2 IO71RSB2 IO66RSB2 NC TCK VPUMP TRST GDA0/IO60VDB1 GEA1/IO98PDB3 GEA0/IO98NDB3 NC GEC2/IO95RSB2 IO91RSB2 IO88RSB2 IO84RSB2 IO80RSB2 IO77RSB2 IO72RSB2 IO68RSB2 IO65RSB2 GDB2/IO62RSB2 TDI NC TDO GND IO94RSB2 GEB2/IO96RSB2 IO93RSB2 IO90RSB2
256-Pin FBGA Pin Number T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 A3P250 Function IO87RSB2 IO83RSB2 IO79RSB2 IO78RSB2 IO73RSB2 IO70RSB2 GDC2/IO63RSB2 IO67RSB2 GDA2/IO61RSB2 TMS GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -3 2
Advanced v0.5
ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 A3P400 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO14RSB0 IO18RSB0 IO22RSB0 IO27RSB0 IO30RSB0 IO39RSB0 IO41RSB0 IO46RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND GAB2/IO154PDB3 GAA2/IO155PPB3 IO10RSB0 GAB1/IO03RSB0 IO12RSB0 IO16RSB0 IO21RSB0 IO26RSB0 IO31RSB0 IO37RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO48RSB0 GBA2/IO60PPB1 IO50RSB0 IO154NDB3 IO08RSB0 IO07RSB0 IO06RSB0 GAC0/IO04RSB0
256-Pin FBGA* Pin Number C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 A3P400 Function GAC1/IO05RSB0 IO20RSB0 IO25RSB0 IO32RSB0 IO38RSB0 IO44RSB0 GBC0/IO54RSB0 IO51RSB0 IO52RSB0 IO53RSB0 IO60NPB1 IO152NPB3 IO155NPB3 GAC2/IO153PDB3 IO09RSB0 GNDQ IO15RSB0 IO19RSB0 IO24RSB0 IO33RSB0 IO40RSB0 IO43RSB0 GNDQ IO49RSB0 GBB2/IO61PDB1 IO63NDB1 IO64NDB1 IO151PDB3 IO152PPB3 IO153NDB3 IO11RSB0 VMV0 VCCIB0 VCCIB0 IO28RSB0 IO35RSB0 VCCIB0
256-Pin FBGA* Pin Number E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 A3P400 Function VCCIB0 VMV1 GBC2/IO62PDB1 IO61NDB1 IO63PDB1 IO64PDB1 IO151NDB3 IO150PPB3 NC IO148PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 NC IO65RSB1 IO73NDB1 IO150NPB3 IO149PDB3 IO149NDB3 GFC1/IO147PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO67PPB1 IO66NDB1 IO66PDB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 A3P400 Function IO73PDB1 GFB0/IO146NPB3 GFA0/IO145NDB3 GFB1/IO146PPB3 VCOMPLF GFC0/IO147NPB3 VCC GND GND GND GND VCC GCC0/IO67NPB1 GCB1/IO68PPB1 GCA0/IO69NPB1 NC GCB0/IO68NPB1 GFA2/IO144PPB3 GFA1/IO145PDB3 VCCPLF IO148NPB3 GFB2/IO143PPB3 VCC GND GND GND GND VCC GCB2/IO71PPB1 GCA1/IO69PPB1 GCC2/IO72PDB1 NC GCA2/IO70PDB1 GFC2/IO142PDB3 IO144NPB3 IO143NPB3 IO138PDB3
256-Pin FBGA* Pin Number K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 A3P400 Function VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO71NPB1 IO72NDB1 IO74RSB1 IO70NDB1 IO142NDB3 IO140NDB3 IO139RSB3 IO138NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB0 GDB0/IO78NPB1 IO75NDB1 IO75PDB1 IO76PDB1 IO141NDB3 IO140PDB3 IO127RSB2 GEC0/IO137NPB3 VMV3 VCCIB2 VCCIB2 IO106RSB2 IO99RSB2
256-Pin FBGA* Pin Number M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 A3P400 Function VCCIB2 VCCIB2 VMV2 IO85RSB2 GDB1/IO78PPB1 GDC1/IO77PDB1 IO76NDB1 IO141PDB3 IO131RSB2 GEC1/IO137PPB3 IO128RSB2 GNDQ GEA2/IO134RSB2 IO113RSB2 IO109RSB2 IO100RSB2 IO95RSB2 IO90RSB2 GNDQ IO83RSB2 VJTAG GDC0/IO77NDB1 GDA1/IO79PDB1 GEB1/IO136PDB3 GEB0/IO136NDB3 IO130RSB2 IO129RSB2 IO126RSB2 IO121RSB2 IO115RSB2 IO108RSB2 IO101RSB2 IO94RSB2 IO88RSB2 IO84RSB2 TCK VPUMP
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 A3P400 Function TRST GDA0/IO79NDB1 GEA1/IO135PDB3 GEA0/IO135NDB3 IO125RSB2 GEC2/IO132RSB2 IO122RSB2 IO118RSB2 IO112RSB2 IO107RSB2 IO102RSB2 IO96RSB2 IO91RSB2 IO87RSB2 GDB2/IO81RSB2 TDI NC TDO GND IO124RSB2 GEB2/IO133RSB2 IO123RSB2 IO120RSB2 IO116RSB2 IO111RSB2 IO105RSB2 IO103RSB2 IO97RSB2 IO93RSB2 GDC2/IO82RSB2 IO86RSB2 GDA2/IO80RSB2 TMS GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 A3P600 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO12RSB0 IO14RSB0 IO19RSB0 IO26RSB0 IO31RSB0 IO37RSB0 IO41RSB0 IO47RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND GAB2/IO169PDB3 GAA2/IO170PDB3 GNDQ GAB1/IO03RSB0 IO10RSB0 IO15RSB0 IO18RSB0 IO24RSB0 IO32RSB0 IO40RSB0 IO43RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO49RSB0 GBA2/IO60PDB1 IO60NDB1 IO169NDB3 IO170NDB3 VMV3 IO06RSB0 GAC0/IO04RSB0
256-Pin FBGA* Pin Number C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 A3P600 Function GAC1/IO05RSB0 IO17RSB0 IO25RSB0 IO33RSB0 IO38RSB0 IO42RSB0 GBC0/IO54RSB0 IO52RSB0 IO51RSB0 IO50RSB0 IO61NPB1 IO166NDB3 IO166PDB3 GAC2/IO168PDB3 IO168NDB3 GNDQ IO13RSB0 IO16RSB0 IO22RSB0 IO36RSB0 IO39RSB0 IO46RSB0 GNDQ IO53RSB0 GBB2/IO61PPB1 IO63PPB1 IO65PDB1 IO165NDB3 IO165PDB3 IO167PDB3 IO167NDB3 VMV0 VCCIB0 VCCIB0 IO29RSB0 IO30RSB0 VCCIB0
256-Pin FBGA* Pin Number E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 A3P600 Function VCCIB0 VMV1 GBC2/IO62PDB1 IO63NPB1 IO64PPB1 IO65NDB1 IO154PSB3 IO162PPB3 IO164PDB3 IO164NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO64NPB1 IO66PPB1 IO67PPB1 IO155NDB3 IO155PDB3 IO162NPB3 GFC1/IO161PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO68PPB1 IO66NPB1 IO67NPB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 A3P600 Function IO71NPB1 GFB0/IO160NPB3 GFA0/IO159NDB3 GFB1/IO160PPB3 VCOMPLF GFC0/IO161NPB3 VCC GND GND GND GND VCC GCC0/IO68NPB1 GCB1/IO69PPB1 GCA0/IO70NPB1 IO73NPB1 GCB0/IO69NPB1 GFA2/IO158PPB3 GFA1/IO159PDB3 VCCPLF IO157NDB3 GFB2/IO157PDB3 VCC GND GND GND GND VCC GCB2/IO72PPB1 GCA1/IO70PPB1 GCC2/IO73PPB1 IO77PPB1 GCA2/IO71PPB1 GFC2/IO156PPB3 IO158NPB3 IO151PDB3 IO151NDB3
256-Pin FBGA* Pin Number K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 A3P600 Function VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO72NPB1 IO82PDB1 IO79PDB1 IO77NPB1 IO149PDB3 IO156NPB3 IO147PDB3 IO147NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO85NPB1 IO82NDB1 IO79NDB1 IO80PDB1 IO149NDB3 IO146PDB3 IO146NDB3 GEC0/IO144NPB3 VMV3 VCCIB2 VCCIB2 IO111RSB2 IO110RSB2
256-Pin FBGA* Pin Number M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 A3P600 Function VCCIB2 VCCIB2 VMV2 IO81NDB1 GDB1/IO85PPB1 GDC1/IO84PDB1 IO80NDB1 IO145PDB3 IO145NDB3 GEC1/IO144PPB3 IO137RSB2 GNDQ GEA2/IO141RSB2 IO120RSB2 IO113RSB2 IO106RSB2 IO99RSB2 IO94RSB2 GNDQ IO81PDB1 VJTAG GDC0/IO84NDB1 GDA1/IO86PDB1 GEB1/IO143PDB3 GEB0/IO143NDB3 IO138RSB2 IO135RSB2 IO134RSB2 IO128RSB2 IO121RSB2 IO115RSB2 IO108RSB2 IO100RSB2 IO95RSB2 VMV1 TCK VPUMP
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 A3P600 Function TRST GDA0/IO86NDB1 GEA1/IO142PDB3 GEA0/IO142NDB3 IO136RSB2 GEC2/IO139RSB2 IO130RSB2 IO125RSB2 IO119RSB2 IO114RSB2 IO107RSB2 IO101RSB2 IO96RSB2 IO90RSB2 GDB2/IO88RSB2 TDI GNDQ TDO GND IO133RSB2 GEB2/IO140RSB2 IO132RSB2 IO127RSB2 IO123RSB2 IO117RSB2 IO112RSB2 IO109RSB2 IO102RSB2 IO97RSB2 GDC2/IO89RSB2 IO91RSB2 GDA2/IO87RSB2 TMS GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 A3P1000 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO22RSB0 IO28RSB0 IO35RSB0 IO45RSB0 IO50RSB0 IO55RSB0 IO61RSB0 GBB1/IO75RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GND GAB2/IO224PDB3 GAA2/IO225PDB3 GNDQ GAB1/IO03RSB0 IO17RSB0 IO21RSB0 IO27RSB0 IO34RSB0 IO44RSB0 IO51RSB0 IO57RSB0 GBC1/IO73RSB0 GBB0/IO74RSB0 IO71RSB0 GBA2/IO78PDB1 IO81PDB1 IO224NDB3 IO225NDB3 VMV3 IO11RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0
256-Pin FBGA* Pin Number C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 A3P1000 Function IO25RSB0 IO36RSB0 IO42RSB0 IO49RSB0 IO56RSB0 GBC0/IO72RSB0 IO62RSB0 VMV0 IO78NDB1 IO81NDB1 IO222NDB3 IO222PDB3 GAC2/IO223PDB3 IO223NDB3 GNDQ IO23RSB0 IO29RSB0 IO33RSB0 IO46RSB0 IO52RSB0 IO60RSB0 GNDQ IO80NDB1 GBB2/IO79PDB1 IO79NDB1 IO82NSB1 IO217PDB3 IO218PDB3 IO221NDB3 IO221PDB3 VMV0 VCCIB0 VCCIB0 IO38RSB0 IO47RSB0 VCCIB0 VCCIB0 VMV1
256-Pin FBGA* Pin Number E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 A3P1000 Function GBC2/IO80PDB1 IO83PPB1 IO86PPB1 IO87PDB1 IO217NDB3 IO218NDB3 IO216PDB3 IO216NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO83NPB1 IO86NPB1 IO90PPB1 IO87NDB1 IO210PSB3 IO213NDB3 IO213PDB3 GFC1/IO209PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO91PPB1 IO90NPB1 IO88PDB1 IO88NDB1 GFB0/IO208NPB3 GFA0/IO207NDB3
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 A3P1000 Function GFB1/IO208PPB3 VCOMPLF GFC0/IO209NPB3 VCC GND GND GND GND VCC GCC0/IO91NPB1 GCB1/IO92PPB1 GCA0/IO93NPB1 IO96NPB1 GCB0/IO92NPB1 GFA2/IO206PSB3 GFA1/IO207PDB3 VCCPLF IO205NDB3 GFB2/IO205PDB3 VCC GND GND GND GND VCC GCB2/IO95PPB1 GCA1/IO93PPB1 GCC2/IO96PPB1 IO100PPB1 GCA2/IO94PSB1 GFC2/IO204PDB3 IO204NDB3 IO203NDB3 IO203PDB3 VCCIB3 VCC GND GND
256-Pin FBGA* Pin Number K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 A3P1000 Function GND GND VCC VCCIB1 IO95NPB1 IO100NPB1 IO102NDB1 IO102PDB1 IO202NDB3 IO202PDB3 IO196PPB3 IO193PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO112NPB1 IO106NDB1 IO106PDB1 IO107PDB1 IO197NSB3 IO196NPB3 IO193NPB3 GEC0/IO190NPB3 VMV3 VCCIB2 VCCIB2 IO147RSB2 IO136RSB2 VCCIB2 VCCIB2 VMV2 IO110NDB1 GDB1/IO112PPB1
256-Pin FBGA* Pin Number M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 A3P1000 Function GDC1/IO111PDB1 IO107NDB1 IO194PSB3 IO192PPB3 GEC1/IO190PPB3 IO192NPB3 GNDQ GEA2/IO187RSB2 IO161RSB2 IO155RSB2 IO141RSB2 IO129RSB2 IO124RSB2 GNDQ IO110PDB1 VJTAG GDC0/IO111NDB1 GDA1/IO113PDB1 GEB1/IO189PDB3 GEB0/IO189NDB3 VMV2 IO179RSB2 IO171RSB2 IO165RSB2 IO159RSB2 IO151RSB2 IO137RSB2 IO134RSB2 IO128RSB2 VMV1 TCK VPUMP TRST GDA0/IO113NDB1 GEA1/IO188PDB3 GEA0/IO188NDB3 IO184RSB2 GEC2/IO185RSB2
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
256-Pin FBGA* Pin Number R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 A3P1000 Function IO168RSB2 IO163RSB2 IO157RSB2 IO149RSB2 IO143RSB2 IO138RSB2 IO131RSB2 IO125RSB2 GDB2/IO115RSB2 TDI GNDQ TDO GND IO183RSB2 GEB2/IO186RSB2 IO172RSB2 IO170RSB2 IO164RSB2 IO158RSB2 IO153RSB2 IO142RSB2 IO135RSB2 IO130RSB2 GDC2/IO116RSB2 IO120RSB2 GDA2/IO114RSB2 TMS GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
484-Pin FBGA
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G H J K L M N P R T U V W Y AA AB
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 A3P400 Function GND GND VCCIB0 NC NC IO13RSB0 IO17RSB0 NC NC IO23RSB0 IO29RSB0 IO34RSB0 IO36RSB0 NC NC IO45RSB0 IO47RSB0 NC NC VCCIB0 GND GND GND VCCIB3 NC NC NC NC NC NC NC NC NC NC NC NC
484-Pin FBGA* Pin Number B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 A3P400 Function NC NC NC NC NC NC VCCIB1 GND VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC VCC NC NC GND NC NC NC VCCIB1 NC NC NC GND GAA0/IO00RSB0 GAA1/IO01RSB0
484-Pin FBGA* Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 A3P400 Function GAB0/IO02RSB0 IO14RSB0 IO18RSB0 IO22RSB0 IO27RSB0 IO30RSB0 IO39RSB0 IO41RSB0 IO46RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND NC NC NC NC NC GND GAB2/IO154PDB3 GAA2/IO155PPB3 IO10RSB0 GAB1/IO03RSB0 IO12RSB0 IO16RSB0 IO21RSB0 IO26RSB0 IO31RSB0 IO37RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO48RSB0 GBA2/IO60PPB1 IO50RSB0 GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P400 Function NC NC NC NC NC IO154NDB3 IO08RSB0 IO07RSB0 IO06RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO20RSB0 IO25RSB0 IO32RSB0 IO38RSB0 IO44RSB0 GBC0/IO54RSB0 IO51RSB0 IO52RSB0 IO53RSB0 IO60NPB1 NC NC NC NC NC NC IO152NPB3 IO155NPB3 GAC2/IO153PDB3 IO09RSB0 GNDQ IO15RSB0 IO19RSB0 IO24RSB0 IO33RSB0
484-Pin FBGA* Pin Number G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 A3P400 Function IO40RSB0 IO43RSB0 GNDQ IO49RSB0 GBB2/IO61PDB1 IO63NDB1 IO64NDB1 NC NC NC NC NC VCC IO151PDB3 IO152PPB3 IO153NDB3 IO11RSB0 VMV0 VCCIB0 VCCIB0 IO28RSB0 IO35RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO61NDB1 IO63PDB1 IO64PDB1 VCC NC NC NC NC NC IO151NDB3
484-Pin FBGA* Pin Number J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 A3P400 Function IO150PPB3 NC IO148PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 NC IO65RSB1 IO73NDB1 NC NC NC NC NC NC IO150NPB3 IO149PDB3 IO149NDB3 GFC1/IO147PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO67PPB1 IO66NDB1 IO66PDB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 A3P400 Function IO73PDB1 NC NC NC NC NC NC GFB0/IO146NPB3 GFA0/IO145NDB3 GFB1/IO146PPB3 VCOMPLF GFC0/IO147NPB3 VCC GND GND GND GND VCC GCC0/IO67NPB1 GCB1/IO68PPB1 GCA0/IO69NPB1 NC GCB0/IO68NPB1 NC NC NC NC NC NC GFA2/IO144PPB3 GFA1/IO145PDB3 VCCPLF IO148NPB3 GFB2/IO143PPB3 VCC GND
484-Pin FBGA* Pin Number M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 A3P400 Function GND GND GND VCC GCB2/IO71PPB1 GCA1/IO69PPB1 GCC2/IO72PDB1 NC GCA2/IO70PDB1 NC NC NC NC NC NC GFC2/IO142PDB3 IO144NPB3 IO143NPB3 IO138PDB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO71NPB1 IO72NDB1 IO74RSB1 IO70NDB1 NC NC NC NC NC
484-Pin FBGA* Pin Number P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 A3P400 Function NC IO142NDB3 IO140NDB3 IO139RSB3 IO138NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO78NPB1 IO75NDB1 IO75PDB1 IO76PDB1 NC NC NC NC NC VCC IO141NDB3 IO140PDB3 IO127RSB2 GEC0/IO137NPB3 VMV3 VCCIB2 VCCIB2 IO106RSB2 IO99RSB2 VCCIB2 VCCIB2 VMV2 IO85RSB2
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 A3P400 Function GDB1/IO78PPB1 GDC1/IO77PDB1 IO76NDB1 VCC NC NC NC NC NC IO141PDB3 IO131RSB2 GEC1/IO137PPB3 IO128RSB2 GNDQ GEA2/IO134RSB2 IO113RSB2 IO109RSB2 IO100RSB2 IO95RSB2 IO90RSB2 GNDQ IO83RSB2 VJTAG GDC0/IO77NDB1 GDA1/IO79PDB1 NC NC NC NC NC NC GEB1/IO136PDB3 GEB0/IO136NDB3 IO130RSB2 IO129RSB2 IO126RSB2
484-Pin FBGA* Pin Number U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 A3P400 Function IO121RSB2 IO115RSB2 IO108RSB2 IO101RSB2 IO94RSB2 IO88RSB2 IO84RSB2 TCK VPUMP TRST GDA0/IO79NDB1 NC NC NC NC NC GND GEA1/IO135PDB3 GEA0/IO135NDB3 IO125RSB2 GEC2/IO132RSB2 IO122RSB2 IO118RSB2 IO112RSB2 IO107RSB2 IO102RSB2 IO96RSB2 IO91RSB2 IO87RSB2 GDB2/IO81RSB2 TDI NC TDO GND NC NC
484-Pin FBGA* Pin Number W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 A3P400 Function NC NC NC GND IO124RSB2 GEB2/IO133RSB2 IO123RSB2 IO120RSB2 IO116RSB2 IO111RSB2 IO105RSB2 IO103RSB2 IO97RSB2 IO93RSB2 GDC2/IO82RSB2 IO86RSB2 GDA2/IO80RSB2 TMS GND NC NC NC VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 A3P400 Function VCC NC NC GND NC NC NC VCCIB1 GND VCCIB3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIB1 GND GND GND VCCIB2 NC NC IO119RSB2
484-Pin FBGA* Pin Number AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 A3P400 Function IO117RSB2 IO114RSB2 IO110RSB2 NC NC IO104RSB2 IO98RSB2 NC NC IO92RSB2 IO89RSB2 NC NC VCCIB2 GND GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 A3P600 Function GND GND VCCIB0 NC NC IO08RSB0 IO09RSB0 NC NC IO21RSB0 IO23RSB0 IO27RSB0 IO28RSB0 NC NC IO35RSB0 IO45RSB0 NC NC VCCIB0 GND GND GND VCCIB3 NC NC NC IO07RSB0 IO11RSB0 NC NC IO20RSB0 NC NC IO34RSB0 NC
484-Pin FBGA* Pin Number B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 A3P600 Function NC IO44RSB0 IO48RSB0 NC NC NC VCCIB1 GND VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC VCC NC NC GND NC NC NC VCCIB1 NC NC NC GND GAA0/IO00RSB0 GAA1/IO01RSB0
484-Pin FBGA* Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 A3P600 Function GAB0/IO02RSB0 IO12RSB0 IO14RSB0 IO19RSB0 IO26RSB0 IO31RSB0 IO37RSB0 IO41RSB0 IO47RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND NC NC NC NC NC GND GAB2/IO169PDB3 GAA2/IO170PDB3 GNDQ GAB1/IO03RSB0 IO10RSB0 IO15RSB0 IO18RSB0 IO24RSB0 IO32RSB0 IO40RSB0 IO43RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO49RSB0 GBA2/IO60PDB1 IO60NDB1 GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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Advanced v0.5
ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P600 Function NC NC NC NC NC IO169NDB3 IO170NDB3 VMV3 IO06RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO17RSB0 IO25RSB0 IO33RSB0 IO38RSB0 IO42RSB0 GBC0/IO54RSB0 IO52RSB0 IO51RSB0 IO50RSB0 IO61NPB1 NC NC NC IO163NDB3 IO163PDB3 NC IO166NDB3 IO166PDB3 GAC2/IO168PDB3 IO168NDB3 GNDQ IO13RSB0 IO16RSB0 IO22RSB0 IO36RSB0
484-Pin FBGA* Pin Number G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 A3P600 Function IO39RSB0 IO46RSB0 GNDQ IO53RSB0 GBB2/IO61PPB1 IO63PPB1 IO65PDB1 NC NC NC NC NC VCC IO165NDB3 IO165PDB3 IO167PDB3 IO167NDB3 VMV0 VCCIB0 VCCIB0 IO29RSB0 IO30RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO63NPB1 IO64PPB1 IO65NDB1 VCC NC NC IO153PDB3 IO154NDB3 NC IO154PDB3
484-Pin FBGA* Pin Number J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 A3P600 Function IO162PPB3 IO164PDB3 IO164NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO64NPB1 IO66PPB1 IO67PPB1 NC IO74PDB1 IO74NDB1 IO153NDB3 NC NC IO155NDB3 IO155PDB3 IO162NPB3 GFC1/IO161PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO68PPB1 IO66NPB1 IO67NPB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 A3P600 Function IO71NPB1 NC NC IO75PDB1 NC IO152PDB3 NC GFB0/IO160NPB3 GFA0/IO159NDB3 GFB1/IO160PPB3 VCOMPLF GFC0/IO161NPB3 VCC GND GND GND GND VCC GCC0/IO68NPB1 GCB1/IO69PPB1 GCA0/IO70NPB1 IO73NPB1 GCB0/IO69NPB1 NC NC IO75NDB1 NC IO152NDB3 NC GFA2/IO158PPB3 GFA1/IO159PDB3 VCCPLF IO157NDB3 GFB2/IO157PDB3 VCC GND
484-Pin FBGA* Pin Number M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 A3P600 Function GND GND GND VCC GCB2/IO72PPB1 GCA1/IO70PPB1 GCC2/IO73PPB1 IO77PPB1 GCA2/IO71PPB1 NC IO76PDB1 NC IO150PPB3 NC NC GFC2/IO156PPB3 IO158NPB3 IO151PDB3 IO151NDB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO72NPB1 IO82PDB1 IO79PDB1 IO77NPB1 NC IO76NDB1 NC NC IO150NPB3
484-Pin FBGA* Pin Number P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 A3P600 Function NC IO149PDB3 IO156NPB3 IO147PDB3 IO147NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO85NPB1 IO82NDB1 IO79NDB1 IO80PDB1 NC NC IO78PDB1 NC IO148PDB3 VCC IO149NDB3 IO146PDB3 IO146NDB3 GEC0/IO144NPB3 VMV3 VCCIB2 VCCIB2 IO111RSB2 IO110RSB2 VCCIB2 VCCIB2 VMV2 IO81NDB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -5 0
Advanced v0.5
ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 A3P600 Function GDB1/IO85PPB1 GDC1/IO84PDB1 IO80NDB1 VCC IO83PDB1 IO78NDB1 NC IO148NDB3 NC IO145PDB3 IO145NDB3 GEC1/IO144PPB3 IO137RSB2 GNDQ GEA2/IO141RSB2 IO120RSB2 IO113RSB2 IO106RSB2 IO99RSB2 IO94RSB2 GNDQ IO81PDB1 VJTAG GDC0/IO84NDB1 GDA1/IO86PDB1 NC IO83NDB1 NC NC NC NC GEB1/IO143PDB3 GEB0/IO143NDB3 IO138RSB2 IO135RSB2 IO134RSB2
484-Pin FBGA* Pin Number U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 A3P600 Function IO128RSB2 IO121RSB2 IO115RSB2 IO108RSB2 IO100RSB2 IO95RSB2 VMV1 TCK VPUMP TRST GDA0/IO86NDB1 NC NC NC NC NC GND GEA1/IO142PDB3 GEA0/IO142NDB3 IO136RSB2 GEC2/IO139RSB2 IO130RSB2 IO125RSB2 IO119RSB2 IO114RSB2 IO107RSB2 IO101RSB2 IO96RSB2 IO90RSB2 GDB2/IO88RSB2 TDI GNDQ TDO GND NC NC
484-Pin FBGA* Pin Number W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 A3P600 Function NC NC NC GND IO133RSB2 GEB2/IO140RSB2 IO132RSB2 IO127RSB2 IO123RSB2 IO117RSB2 IO112RSB2 IO109RSB2 IO102RSB2 IO97RSB2 GDC2/IO89RSB2 IO91RSB2 GDA2/IO87RSB2 TMS GND NC NC NC VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 A3P600 Function VCC NC NC GND NC NC NC VCCIB1 GND VCCIB3 NC NC NC IO131RSB2 IO126RSB2 NC NC IO116RSB2 NC NC IO103RSB2 NC NC IO93RSB2 NC NC NC NC VCCIB1 GND GND GND VCCIB2 NC NC IO129RSB2
484-Pin FBGA* Pin Number AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 A3P600 Function IO124RSB2 IO122RSB2 IO118RSB2 NC NC IO105RSB2 IO104RSB2 NC NC IO98RSB2 IO92RSB2 NC NC VCCIB2 GND GND
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -5 2
Advanced v0.5
ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 A3P1000 Function GND GND VCCIB0 IO07RSB0 IO09RSB0 IO13RSB0 IO18RSB0 IO20RSB0 IO26RSB0 IO32RSB0 IO40RSB0 IO41RSB0 IO53RSB0 IO59RSB0 IO64RSB0 IO65RSB0 IO67RSB0 IO69RSB0 NC VCCIB0 GND GND GND VCCIB3 NC IO181RSB2 IO178RSB2 IO175RSB2 IO169RSB2 IO166RSB2 IO160RSB2 IO152RSB2 IO146RSB2 IO139RSB2 IO133RSB2
484-Pin FBGA* Pin Number AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 A3P1000 Function NC NC IO122RSB2 IO119RSB2 IO117RSB2 NC NC VCCIB1 GND GND GND VCCIB2 IO180RSB2 IO176RSB2 IO173RSB2 IO167RSB2 IO162RSB2 IO156RSB2 IO150RSB2 IO145RSB2 IO144RSB2 IO132RSB2 IO127RSB2 IO126RSB2 IO123RSB2 IO121RSB2 IO118RSB2 NC VCCIB2 GND GND GND VCCIB3 NC IO06RSB0
484-Pin FBGA* Pin Number B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 A3P1000 Function IO08RSB0 IO12RSB0 IO15RSB0 IO19RSB0 IO24RSB0 IO31RSB0 IO39RSB0 IO48RSB0 IO54RSB0 IO58RSB0 IO63RSB0 IO66RSB0 IO68RSB0 IO70RSB0 NC NC VCCIB1 GND VCCIB3 IO220PDB3 NC NC GND IO10RSB0 IO14RSB0 VCC VCC IO30RSB0 IO37RSB0 IO43RSB0 NC VCC VCC NC NC
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 A3P1000 Function GND NC NC NC VCCIB1 IO219PDB3 IO220NDB3 NC GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO22RSB0 IO28RSB0 IO35RSB0 IO45RSB0 IO50RSB0 IO55RSB0 IO61RSB0 GBB1/IO75RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GND NC NC NC IO219NDB3 NC GND GAB2/IO224PDB3 GAA2/IO225PDB3 GNDQ GAB1/IO03RSB0 IO17RSB0
484-Pin FBGA* Pin Number E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 A3P1000 Function IO21RSB0 IO27RSB0 IO34RSB0 IO44RSB0 IO51RSB0 IO57RSB0 GBC1/IO73RSB0 GBB0/IO74RSB0 IO71RSB0 GBA2/IO78PDB1 IO81PDB1 GND NC IO84PDB1 NC IO215PDB3 IO215NDB3 IO224NDB3 IO225NDB3 VMV3 IO11RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO25RSB0 IO36RSB0 IO42RSB0 IO49RSB0 IO56RSB0 GBC0/IO72RSB0 IO62RSB0 VMV0 IO78NDB1 IO81NDB1 IO82PPB1 NC
484-Pin FBGA* Pin Number F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 A3P1000 Function IO84NDB1 IO214NDB3 IO214PDB3 NC IO222NDB3 IO222PDB3 GAC2/IO223PDB3 IO223NDB3 GNDQ IO23RSB0 IO29RSB0 IO33RSB0 IO46RSB0 IO52RSB0 IO60RSB0 GNDQ IO80NDB1 GBB2/IO79PDB1 IO79NDB1 IO82NPB1 IO85PDB1 IO85NDB1 NC NC NC VCC IO217PDB3 IO218PDB3 IO221NDB3 IO221PDB3 VMV0 VCCIB0 VCCIB0 IO38RSB0 IO47RSB0
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -5 4
Advanced v0.5
ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 A3P1000 Function VCCIB0 VCCIB0 VMV1 GBC2/IO80PDB1 IO83PPB1 IO86PPB1 IO87PDB1 VCC NC NC IO212NDB3 IO212PDB3 NC IO217NDB3 IO218NDB3 IO216PDB3 IO216NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO83NPB1 IO86NPB1 IO90PPB1 IO87NDB1 NC IO89PDB1 IO89NDB1 IO211PDB3 IO211NDB3 NC
484-Pin FBGA* Pin Number K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 A3P1000 Function IO210PPB3 IO213NDB3 IO213PDB3 GFC1/IO209PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO91PPB1 IO90NPB1 IO88PDB1 IO88NDB1 IO94NPB1 IO98NDB1 IO98PDB1 NC IO200PDB3 IO210NPB3 GFB0/IO208NPB3 GFA0/IO207NDB3 GFB1/IO208PPB3 VCOMPLF GFC0/IO209NPB3 VCC GND GND GND GND VCC GCC0/IO91NPB1 GCB1/IO92PPB1
484-Pin FBGA* Pin Number L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 A3P1000 Function GCA0/IO93NPB1 IO96NPB1 GCB0/IO92NPB1 IO97PDB1 IO97NDB1 IO99NPB1 NC IO200NDB3 IO206NDB3 GFA2/IO206PDB3 GFA1/IO207PDB3 VCCPLF IO205NDB3 GFB2/IO205PDB3 VCC GND GND GND GND VCC GCB2/IO95PPB1 GCA1/IO93PPB1 GCC2/IO96PPB1 IO100PPB1 GCA2/IO94PPB1 IO101PPB1 IO99PPB1 NC IO201NDB3 IO201PDB3 NC GFC2/IO204PDB3 IO204NDB3 IO203NDB3 IO203PDB3
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 A3P1000 Function VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO95NPB1 IO100NPB1 IO102NDB1 IO102PDB1 NC IO101NPB1 IO103PDB1 NC IO199PDB3 IO199NDB3 IO202NDB3 IO202PDB3 IO196PPB3 IO193PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO112NPB1 IO106NDB1 IO106PDB1 IO107PDB1 NC
484-Pin FBGA* Pin Number P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 A3P1000 Function IO104PDB1 IO103NDB1 NC IO197PPB3 VCC IO197NPB3 IO196NPB3 IO193NPB3 GEC0/IO190NPB3 VMV3 VCCIB2 VCCIB2 IO147RSB2 IO136RSB2 VCCIB2 VCCIB2 VMV2 IO110NDB1 GDB1/IO112PPB1 GDC1/IO111PDB1 IO107NDB1 VCC IO104NDB1 IO105PDB1 IO198PDB3 IO198NDB3 NC IO194PPB3 IO192PPB3 GEC1/IO190PPB3 IO192NPB3 GNDQ GEA2/IO187RSB2 IO161RSB2 IO155RSB2
484-Pin FBGA* Pin Number T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 A3P1000 Function IO141RSB2 IO129RSB2 IO124RSB2 GNDQ IO110PDB1 VJTAG GDC0/IO111NDB1 GDA1/IO113PDB1 NC IO108PDB1 IO105NDB1 IO195PDB3 IO195NDB3 IO194NPB3 GEB1/IO189PDB3 GEB0/IO189NDB3 VMV2 IO179RSB2 IO171RSB2 IO165RSB2 IO159RSB2 IO151RSB2 IO137RSB2 IO134RSB2 IO128RSB2 VMV1 TCK VPUMP TRST GDA0/IO113NDB1 NC IO108NDB1 IO109PDB1 NC NC
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
4 -5 6
Advanced v0.5
ProASIC3 Flash Family FPGAs
484-Pin FBGA* Pin Number V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 A3P1000 Function GND GEA1/IO188PDB3 GEA0/IO188NDB3 IO184RSB2 GEC2/IO185RSB2 IO168RSB2 IO163RSB2 IO157RSB2 IO149RSB2 IO143RSB2 IO138RSB2 IO131RSB2 IO125RSB2 GDB2/IO115RSB2 TDI GNDQ TDO GND NC IO109NDB1 NC IO191PDB3 NC GND IO183RSB2 GEB2/IO186RSB2 IO172RSB2 IO170RSB2 IO164RSB2 IO158RSB2 IO153RSB2 IO142RSB2 IO135RSB2 IO130RSB2 GDC2/IO116RSB2
484-Pin FBGA* Pin Number W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 A3P1000 Function IO120RSB2 GDA2/IO114RSB2 TMS GND NC NC NC VCCIB3 IO191NDB3 NC IO182RSB2 GND IO177RSB2 IO174RSB2 VCC VCC IO154RSB2 IO148RSB2 IO140RSB2 NC VCC VCC NC NC GND NC NC NC VCCIB1
Note: *Refer to the "User I/O Naming Convention" section on page 2-46.
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ProASIC3 Flash Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Advanced v0.4 Changes in Current Version (Advanced v0.5) The "I/Os Per Package" was updated for the following devices and packages Device Package A3P250/M7ACP250 VQ100 A3P250/M7ACP250 FG144 A3P1000 FG256 M7 device information is new. The I/O counts in the "I/Os Per Package" table were updated. The "Security" section was updated to include information concerning M7 ProASIC3 AES support. In the "PLL and Clock Conditioning Circuitry (CCC)" section, the low jitter bullet was updated. Table 2-2 was updated to include the number of rows in each top or bottom spine. EXTFB was removed from Figure 2-14. The "PLL Macro" section was updated. EXTFB information was removed from this section. EXTFB was removed from Figure 2-17. The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 2-4. EXTFB was removed from Figure 2-19. The "Hot-Swap Support" section was updated. Table 2-15 was updated. The "Cold-Sparing Support" section was updated. The "Electrostatic Discharge (ESD) Protection" section was updated. The LVPECL specification in Table 2-16 was updated. In the Bank 1 area of Figure 2-36, VMV2 was changed to VMV1 and VCCIB2 was changed to VCCIB1. The "JTAG Pins" were updated. The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions" section The "128-Bit AES Decryption" section was updated to include M7 device information. Table 3-6 was updated. Table 3-7 was updated. In Table 3-10 PAC4 was updated. Table 3-17 was updated. The note in Table 3-23 was updated. All Timing Characteristic tables were updated from LVTTL to Register Delays. The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated. The data for FTCKMAX was updated in Table 3-71. ii 1-1 1-5 2-11 2-16 2-17 2-19 2-20 2-21 2-35 2-35 2-36 2-36 2-36 2-46 2-49 2-48 2-50 3-4 3-5 3-6 3-15 3-17 3-19 to 3-44 3-54 to 3-58 3-59 Page ii
Advanced v0.3
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Previous Version Advanced v0.2
Changes in Current Version (Advanced v0.5) The A3P1000 table was updated in the "208-Pin PQFP*". The A3P1000 table was updated in the "144-Pin FBGA*". The A3P1000 table was updated in the "256-Pin FBGA*". The A3P1000 table was updated in the "484-Pin FBGA*". The "I/Os Per Package" table was updated. The "Live at Power-Up" is new. Figure 2-5 was updated. The "Clock Resources (VersaNets)" was updated. The "VersaNet Global Networks and Spine Access" was updated. The "PLL Macro" was updated. Figure 2-17 was updated. Figure 2-19 was updated. Table 2-6 was updated. Table 2-7 was updated. The "FIFO Flag Usage Considerations" was updated. Table 2-13 was updated. Figure 2-23 was updated. The "Cold-Sparing Support" is new. Table 2-16 was updated. Table 2-18 was updated. The "User I/O Naming Convention" was updated. Pin descriptions in the "JTAG Pins" section on page 2-49 were updated. Table 3-7 was updated. The "Methodology" section was updated. Table 3-34 and Table 3-35 were updated. The A3P250 "100-Pin VQFP*" pin table was updated. The A3P250 "208-Pin PQFP*" pin table was updated. The A3P250 "144-Pin FBGA*" pin table was updated. The A3P250 "256-Pin FBGA*" pin table was updated.
Page 4-20 4-27 4-39 4-53 ii 1-2 2-6 2-10 2-12 2-17 2-19 2-21 2-26 2-26 2-29 2-30 2-32 2-36 2-36 2-44 2-46 2-48 3-5 3-7 3-23 4-5 4-16 4-25 4-28
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Web-only." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a advanced datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
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